ATA5773-PXQW Atmel, ATA5773-PXQW Datasheet - Page 53
ATA5773-PXQW
Manufacturer Part Number
ATA5773-PXQW
Description
XMITTR UHF ASK/FSK 310MHZ 24VQFN
Manufacturer
Atmel
Datasheet
1.ATA5773-DK1.pdf
(219 pages)
Specifications of ATA5773-PXQW
Frequency
310MHz ~ 350MHz
Modulation Or Protocol
UHF
Power - Output
8dBm
Voltage - Supply
2 V ~ 4 V
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA5x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
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Quantity
Price
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9137E–RKE–12/10
In safety level 1, WDE is overridden by WDRF in MCUSR. See
MCU Status Register” on page 51
set when WDRF is set. To clear WDE, WDRF must be cleared before disabling the Watchdog
with the procedure described above. This feature ensures multiple resets during conditions
causing failure, and a safe start-up after the failure.
Note:
• Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler 3, 2, 1, and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is
enabled. The different prescaling values and their corresponding Timeout Periods are shown
in
Table 4-18.
WDP3
Table 4-18 on page
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
If the watchdog timer is not going to be used in the application, it is important to go through a
watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally
enabled, for example by a runaway pointer or brown-out condition, the device will be reset,
which in turn will lead to a new watchdog reset. To avoid this situation, the application software
should always clear the WDRF flag and the WDE control bit in the initialization routine.
WDP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Watchdog Timer Prescale Select
WDP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
53.
WDP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
for description of WDRF. This means that WDE is always
Number of WDT Oscillator
1024K cycles
128K cycles
256K cycles
512K cycles
16K cycles
32K cycles
64K cycles
2K cycles
4K cycles
8K cycles
Cycles
Atmel ATA5771/73/74
Reserved
Section 4.11.5.1 “MCUSR –
Typical Time-out at
V
CC
0.125 s
16 ms
32 ms
64 ms
0.25 s
8.0 s
0.5 s
1.0 s
2.0 s
4.0 s
= 5.0V
53
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