ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 111

XMITTR UHF ASK/FSK 868MHZ 24VQFN

ATA5771-PXQW

Manufacturer Part Number
ATA5771-PXQW
Description
XMITTR UHF ASK/FSK 868MHZ 24VQFN
Manufacturer
Atmel
Datasheet

Specifications of ATA5771-PXQW

Frequency
868MHz ~ 928MHz
Modulation Or Protocol
UHF
Power - Output
8dBm
Voltage - Supply
2 V ~ 4 V
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA5x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Part Number:
ATA5771-PXQW
Manufacturer:
ATMEL
Quantity:
218
9137E–RKE–12/10
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM.
When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set
accordingly at the same timer clock cycle as the OCR1x Registers are updated with the dou-
ble buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time
the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR1x Registers are written. As the third period shown in
changing the TOP actively while the Timer/Counter is running in the phase correct mode can
result in an unsymmetrical output. The reason for this can be found in the time of update of the
OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at
TOP. This implies that the length of the falling slope is determined by the previous TOP value,
while the length of the rising slope is determined by the new TOP value. When these two val-
ues differ the two slopes of the period will differ in length. The difference in length gives the
unsymmetrical result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1x1:0 to three (See
page
the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or
clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the
counter increments, and clearing (or setting) the OC1x Register at compare match between
OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when
using phase correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
117). The actual OC1x value will only be visible on the port pin if the data direction for
f
OCnxPCPWM
=
---------------------------------
2
f
Atmel ATA5771/73/74
clk_I/O
N
TOP
Figure 4-44 on page 110
Table 4-41 on
illustrates,
111

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