ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 19

XMITTR UHF ASK/FSK 868MHZ 24VQFN

ATA5771-PXQW

Manufacturer Part Number
ATA5771-PXQW
Description
XMITTR UHF ASK/FSK 868MHZ 24VQFN
Manufacturer
Atmel
Datasheet

Specifications of ATA5771-PXQW

Frequency
868MHz ~ 928MHz
Modulation Or Protocol
UHF
Power - Output
8dBm
Voltage - Supply
2 V ~ 4 V
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA5x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA5771-PXQW
Manufacturer:
ATMEL
Quantity:
218
4.7.7
4.7.8
9137E–RKE–12/10
Instruction Execution Timing
Reset and Interrupt Handling
This section describes the general access timing concepts for instruction execution. The
Atmel
clock source for the chip. No internal clock division is used.
Figure 4-5
Harvard architecture and the fast access Register File concept. This is the basic pipelining
concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per
cost, functions per clocks, and functions per power-unit.
Figure 4-5.
Figure 4-6
ALU operation using two register operands is executed, and the result is stored back to the
destination register.
Figure 4-6.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Inter-
rupt Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
55. The list also determines the priority levels of the different interrupts. The lower the address
the higher is the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
1st Instruction Execute
ALU Operation Execute
®
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
AVR
Result Write Back
shows the internal timing concept for the Register File. In a single clock cycle an
shows the parallel instruction fetches and instruction executions enabled by the
®
CPU is driven by the CPU clock clk
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
clk
clk
CPU
CPU
T1
T1
CPU
T2
T2
Atmel ATA5771/73/74
, directly generated from the selected
Section 4.12 “Interrupts” on page
T3
T3
T4
T4
19

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