ATA5771-PXQW Atmel, ATA5771-PXQW Datasheet - Page 63

• Manufacturer Part Number: ATA5771-PXQW
• Description: XMITTR UHF ASK/FSK 868MHZ 24VQFN
• Manufacturer: Atmel

Specifications of ATA5771-PXQW

• Frequency: 868MHz ~ 928MHz
• Modulation Or Protocol: UHF
• Power - Output: 8dBm
• Voltage - Supply: 2 V ~ 4 V
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA5x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Sensitivity: -
• Data Rate - Maximum: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Details

4.14.2.4
9137E–RKE–12/10
Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
ceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay.
shows a timing diagram of the synchronization when reading an externally applied pin value.
The maximum and minimum propagation delays are denoted t
Figure 4-23. Synchronization when Reading an Externally Applied Pin value
Consider the clock period starting shortly after the first falling edge of the system clock. The
latch is closed when the clock is low, and goes transparent when the clock is high, as indi-
cated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the
system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock
edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin
will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in
positive edge of the clock. In this case, the delay tpd through the synchronizer is one system
clock period.
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
Figure 4-24 on page
PINxn
r17
64. The out instruction sets the “SYNC LATCH” signal at the
Figure 4-22 on page
XXX
t
pd, max
0x00
XXX
Atmel ATA5771/73/74
t
61, the PINxn Register bit and the pre-
pd, min
pd,max
in r17, PINx
and t
pd,min
respectively.
0xFF
Figure 4-23
63