ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 13

• Manufacturer Part Number: ATMEGA128RFA1-ZUR
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZUR

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Stack Pointer
RAM Page Z Select
Register – RAMPZ
Instruction
Execution Timing
2467V–AVR–02/11
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
• Bits 7..1 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bit 0 – RAMPZ0: Extended RAM Page Z-pointer
The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z-
pointer. As the ATmega128 does not support more than 64K of SRAM memory, this register is
used only to select which page in the program memory is accessed when the ELPM/SPM
instruction is used. The different settings of the RAMPZ0 bit have the following effects:
Note that LPM is not affected by the RAMPZ setting.
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
RAMPZ0 = 0:
RAMPZ0 = 1:
SP15
R/W
SP7
R/W
15
7
0
0
R
7
–
0
Program memory address $0000 - $7FFF (lower 64 Kbytes) is
accessed by ELPM/SPM
Program memory address $8000 - $FFFF (higher 64 Kbytes) is
accessed by ELPM/SPM
SP14
SP6
R/W
R/W
––
14
R
6
0
0
6
0
SP13
SP5
R/W
R/W
13
5
–
R
0
5
0
0
CPU
, directly generated from the selected clock source for the
SP12
R/W
R/W
SP4
12
R
4
–
0
4
0
0
SP11
R/W
R/W
SP3
R
11
3
–
0
3
0
0
SP10
R/W
SP2
R/W
R
10
2
–
0
2
0
0
SP9
SP1
R/W
R/W
R
1
–
0
9
1
0
0
RAMPZ0
ATmega128
SP8
SP0
R/W
R/W
R/W
8
0
0
0
0
0
RAMPZ
SPH
SPL
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