ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 130

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZUR

Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZUR

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
Timer/Counter
Timing Diagrams
130
ATmega128
The extreme values for the OCRnx Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
If OCRnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the OCnA Output
will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for
modes utilizing double buffering).
Figure 55. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
Figure 56
Figure 56. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
TCNTn
OCRnx
TCNTn
OCRnx
OCFnx
OCFnx
(clk
(clk
clk
clk
clk
clk
I/O
I/O
I/O
I/O
Tn
Tn
shows the same timing data, but with the prescaler enabled.
/1)
/8)
OCRnx - 1
OCRnx - 1
Figure 55
OCRnx
OCRnx
shows a timing diagram for the setting of OCFnx.
OCRnx Value
OCRnx Value
OCRnx + 1
OCRnx + 1
Tn
) is therefore shown as a
OCRnx + 2
OCRnx + 2
clk_I/O
2467V–AVR–02/11
/8)

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