ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 161

• Manufacturer Part Number: ATMEGA128RFA1-ZUR
• Description: IC AVR MCU 2.4GHZ XCEIVER 64QFN
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RFA1-ZUR

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3.5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 12.5mA
• Current - Transmitting: 14.5mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 16kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: ATMEGA128x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 16 KB
• Interface Type: JTAG
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVR128RFA1-EK1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Example
2467V–AVR–02/11
When the modulator is enabled the type of modulation (logical AND or OR) can be selected by
the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the
COMnx1:0 bit setting.
Figure 74
in fast PWM mode (non-inverted) and Timer/Counter2 uses CTC waveform mode with toggle
Compare Output mode (COMnx1:0 = 1).
Figure 74. Output Compare Modulator, Timing Diagram
In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated
by the Output Compare unit C of the Timer/Counter1.
The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is
equal to the number of system clock cycles of one period of the carrier (OC2). In this example
the resolution is reduced by a factor of two. The reason for the reduction is illustrated in
74
high time is one cycle longer than the period 3 high time, but the result on the PB7 output is
equal in both periods.
at the second and third period of the PB7 output when PORTB7 equals zero. The period 2
(FPWM Mode)
(PORTB7 = 0)
(PORTB7 = 1)
(CTC Mode)
(Period)
OC1C
illustrates the modulator in action. In this example the Timer/Counter1 is set to operate
clk
OC2
PB7
PB7
I/O
1
2
ATmega128
3
Figure
161