ATMEGA128RFA1-ZUR Atmel, ATMEGA128RFA1-ZUR Datasheet - Page 262

IC AVR MCU 2.4GHZ XCEIVER 64QFN

ATMEGA128RFA1-ZUR

Manufacturer Part Number
ATMEGA128RFA1-ZUR
Description
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer
Atmel
Series
ATMEGAr

Specifications of ATMEGA128RFA1-ZUR

Frequency
2.4GHz
Data Rate - Maximum
2Mbps
Modulation Or Protocol
802.15.4 Zigbee
Applications
General Purpose
Power - Output
3.5dBm
Sensitivity
-100dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
12.5mA
Current - Transmitting
14.5mA
Data Interface
PCB, Surface Mount
Memory Size
128kB Flash, 4kB EEPROM, 16kB RAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
128 KB
Data Ram Size
16 KB
Interface Type
JTAG
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
38
Number Of Timers
6
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVR128RFA1-EK1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA128RFA1-ZUR
Manufacturer:
ON
Quantity:
56 000
262
ATmega128
Table 104. Boundary-scan Signals for the ADC
Signal
Name
COMP
ACLK
ACTEN
ADCBGEN
ADCEN
AMPEN
DAC_9
DAC_8
DAC_7
DAC_6
DAC_5
DAC_4
DAC_3
DAC_2
DAC_1
DAC_0
EXTCH
G10
G20
GNDEN
HOLD
IREFEN
Direction
as Seen
from the
ADC
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Comparator Output
Clock signal to gain stages
implemented as Switch-
cap filters
Enable path from gain
stages to the comparator
Enable Band-gap
reference as negative
input to comparator
Power-on signal to the
ADC
Power-on signal to the
gain stages
Bit 9 of digital value to DAC
Bit 8 of digital value to DAC
Bit 7 of digital value to DAC
Bit 6 of digital value to DAC
Bit 5 of digital value to DAC
Bit 4 of digital value to DAC
Bit 3 of digital value to DAC
Bit 2 of digital value to DAC
Bit 1 of digital value to DAC
Bit 0 of digital value to DAC
Connect ADC channels 0 -
3 to by-pass path around
gain stages
Enable 10x gain
Enable 20x gain
Ground the negative input
to comparator when true
Sample & Hold signal.
Sample analog signal
when low. Hold signal
when high. If gain stages
are used, this signal must
go active when ACLK is
high.
Enables Band-gap
reference as AREF signal
to DAC
Recommended
Input
when not
in Use
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
Output Values when
Recommended Inputs
are Used, and CPU is
not Using the ADC
2467V–AVR–02/11
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0

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