CYWUSB6934-48LFXC Cypress Semiconductor Corp, CYWUSB6934-48LFXC Datasheet - Page 11

• Manufacturer Part Number: CYWUSB6934-48LFXC
• Description: IC USB WIRELESS 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp
• Type: Transceiverr

Specifications of CYWUSB6934-48LFXC

• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: HID, PC, Peripheral Gaming Devices
• Power - Output: 0dBm
• Sensitivity: -90dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Operating Frequency: 2483 MHz
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1624

Table 10. Receive SERDES Interrupt Status
Document 38-16007 Rev. *J
Bit
Bit
3
2
1
0
7
6
5
Valid B
Underflow A
Overflow A
EOF A
Full A
Valid B
Flow Violation
B
EOF B
7
Name
Addr: 0x08
Name
Flow Violation
The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive
SERDES Data A register (Reg 0x09)
1 = Underflow A interrupt enabled for Receive SERDES Data A
0 = Underflow A interrupt disabled for Receive SERDES Data A
An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when
it is empty.
The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive
SERDES Data A register (0x09)
1 = Overflow A interrupt enabled for Receive SERDES Data A
0 = Overflow A interrupt disabled for Receive SERDES Data A
An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg
0x09) before the prior data is read out.
The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel
A Receiver.
1 = EOF A interrupt enabled for Channel A Receiver.
0 = EOF A interrupt disabled for Channel A Receiver.
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit
has been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field.
If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared
by reading the receive status register.
The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having
data written into it.
1 = Full A interrupt enabled for Receive SERDES Data A
0 = Full A interrupt disabled for Receive SERDES Data A
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data
A register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether
or not a complete byte has been received.
The Valid B bit is true when all the bits in the Receive SERDES Data B register (Reg 0x0B) are valid.
1 = All bits are valid for Receive SERDES Data B.
0 = Not all bits are valid for Receive SERDES Data B.
When data is written into the Receive SERDES Data B register (Reg 0x0B) this bit is set if all of the bits within
the byte that has been written are valid. This bit cannot generate an interrupt.
The Flow Violation B bit is used to signal whether an overflow or underflow condition has occurred for the
Receive SERDES Data B register (Reg 0x0B).
1 = Overflow/underflow interrupt pending for Receive SERDES Data B.
0 = No overflow/underflow interrupt pending for Receive SERDES Data B.
Overflow conditions occur when the radio loads new data into the Receive SERDES Data B register (Reg
0x0B) before the prior data has been read. Underflow conditions occur when trying to read the Receive
SERDES Data B register (Reg 0x0B) when the register is empty. This bit is cleared by reading the Receive
Interrupt Status register (Reg 0x08)
The End of Frame B bit is used to signal whether an EOF event has occurred on the Channel B receive.
1 = EOF interrupt pending for Channel B.
0 = No EOF interrupt pending for Channel B.
An EOF condition occurs for the Channel B Receiver when receive has begun and then the number of bit
times specified in the SERDES Control register (Reg 0x06) elapse without any valid bits being received. This
bit is cleared by reading the Receive Interrupt Status register (Reg 0x08)
B
6
EOF B
5
[4]
Full B
REG_RX_INT_STAT
4
Description
Valid A
Description
3
Flow Violation
A
2
EOF A
1
CYWUSB6934
CYWUSB6932
Default: 0x00
Page 11 of 33
Full A
0
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