IC RF TXRX SNGL-CHIP LP 20-QFN

CC2500-RTR1

Manufacturer Part NumberCC2500-RTR1
DescriptionIC RF TXRX SNGL-CHIP LP 20-QFN
ManufacturerTexas Instruments
CC2500-RTR1 datasheet
 


Specifications of CC2500-RTR1

Frequency2.4GHzData Rate - Maximum500kBaud
Modulation Or Protocol2-FSK, ASK, GFSK, MSK, OOKApplicationsISM, SRD
Power - Output-30dBm ~ 10dBmSensitivity-104dBm
Voltage - Supply1.8 V ~ 3.6 VCurrent - Receiving17mA
Current - Transmitting21.5mA @ 1 dBmData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature-40°C ~ 85°C
Package / Case20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFNOperating Temperature (min)-40C
Operating Temperature (max)85COperating Temperature ClassificationIndustrial
Product Depth (mm)4mmProduct Length (mm)4mm
Operating Supply Voltage (min)1.8VOperating Supply Voltage (typ)2.5/3.3V
Operating Supply Voltage (max)3.6VFor Use With296-24121 - DEV WRLSS TOOL FOR MSP430296-23125 - TARGET BRD WIRELESS EZ430-RF2500296-23031 - DEV WRLSS TOOL FOR MSP430/CC2500296-22903 - KIT EVAL MODULE FOR CC2500296-23077 - KIT DEV FOR CC2500/CC2550
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantMemory Size-
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The GDO0 pin can also be used for an on-chip
analog temperature sensor. By measuring the
voltage on the GDO0 pin with an external ADC,
the
temperature
can
be
Specifications for the temperature sensor are
found in Section 4.7 on page 14.
With default PTEST register setting (0x7F) the
temperature sensor output is only available
when the frequency synthesizer is enabled
(e.g. the MANCAL, FSTXON, RX and TX
states). It is necessary to write 0xBF to the
PTEST register to use the analog temperature
sensor in the IDLE state. Before leaving the
IDLE state, the PTEST register should be
restored to its default value (0x7F).
11.3
Optional Radio Control Feature
The CC2500 has an optional way of controlling
the radio, by reusing SI, SCLK and CSn from
the SPI interface. This feature allows for a
simple three-pin control of the major states of
the radio: SLEEP, IDLE, RX and TX.
This optional functionality is enabled with the
MCSM0.PIN_CTRL_EN configuration bit.
12 Data Rate Programming
The data rate used when transmitting, or the
data rate expected in receive is programmed
by
the
MDMCFG3.DRATE_M
MDMCFG4.DRATE_E configuration registers.
The data rate is given by the formula below.
As the formula shows, the programmed data
rate depends on the crystal frequency.
256
DRATE
_
M
2
R
DATA
28
2
The following approach can be used to find
suitable values for a given data rate:
R
 
DATA
DRATE
_
E
log
2
f
XOSC
R
2
DATA
DRATE
_
M
DRATE
f
2
XOSC
State changes are commanded as follows:
When CSn is high the SI and SCLK is set to
the desired state according to Table 18. When
CSn goes low the state of SI and SCLK is
calculated.
latched and a command strobe is generated
internally according to the control coding. It is
only possible to change state with this
functionality. That means that for instance RX
will not be restarted if SI and SCLK are set to
RX and CSn toggles. When CSn is low the SI
and SCLK has normal SPI functionality.
All pin control command strobes are executed
immediately, except the SPWD strobe, which is
delayed until CSn goes high.
CSn
SCLK
1
0
Table 18: Optional Pin Control Coding
If DRATE_M is rounded to the nearest integer
and becomes 256, increment DRATE_E and
and
the
use DRATE_M=0.
The data rate can be set from 1.2 kBaud to
500 kBaud with the minimum step size of:
Min Data
Rate
DRATE
_
E
[kBaud]
f
XOSC
0.8
3.17
6.35
12.7
25.4
50.8
20
2
 
101.6
203.1
28
406.3
256
_
E
SWRS040C
SI
Function
X
X
Chip unaffected by SCLK/SI
0
0
Generates SPWD strobe
0
1
Generates STX strobe
1
0
Generates SIDLE strobe
1
1
Generates SRX strobe
SPI
SPI
SPI mode (wakes up into
mode
mode
IDLE if in SLEEP/XOFF)
Typical
Max Data
Data Rate
Data Rate
Rate
Step Size
[kBaud]
[kBaud]
[kBaud]
1.2/2.4
3.17
0.0062
4.8
6.35
0.0124
9.6
12.7
0.0248
19.6
25.4
0.0496
38.4
50.8
0.0992
76.8
101.6
0.1984
153.6
203.1
0.3967
250
406.3
0.7935
500
500
1.5869
Table 19: Data Rate Step Size
Page 26 of 89