IC RF TXRX SNGL-CHIP LP 20-QFN

CC2500-RTR1

Manufacturer Part NumberCC2500-RTR1
DescriptionIC RF TXRX SNGL-CHIP LP 20-QFN
ManufacturerTexas Instruments
CC2500-RTR1 datasheet
 


Specifications of CC2500-RTR1

Frequency2.4GHzData Rate - Maximum500kBaud
Modulation Or Protocol2-FSK, ASK, GFSK, MSK, OOKApplicationsISM, SRD
Power - Output-30dBm ~ 10dBmSensitivity-104dBm
Voltage - Supply1.8 V ~ 3.6 VCurrent - Receiving17mA
Current - Transmitting21.5mA @ 1 dBmData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature-40°C ~ 85°C
Package / Case20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFNOperating Temperature (min)-40C
Operating Temperature (max)85COperating Temperature ClassificationIndustrial
Product Depth (mm)4mmProduct Length (mm)4mm
Operating Supply Voltage (min)1.8VOperating Supply Voltage (typ)2.5/3.3V
Operating Supply Voltage (max)3.6VFor Use With296-24121 - DEV WRLSS TOOL FOR MSP430296-23125 - TARGET BRD WIRELESS EZ430-RF2500296-23031 - DEV WRLSS TOOL FOR MSP430/CC2500296-22903 - KIT EVAL MODULE FOR CC2500296-23077 - KIT DEV FOR CC2500/CC2550
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantMemory Size-
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Page 27/96

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13 Receiver Channel Filter Bandwidth
In order to meet different channel width
requirements, the receiver channel filter is
programmable. The MDMCFG4.CHANBW_E and
MDMCFG4.CHANBW_M configuration registers
control the receiver channel filter bandwidth,
which
scales
with
the
crystal
frequency. The following formula gives the
relation between the register settings and the
channel filter bandwidth:
f
XOSC
BW
channel
8
4 (
CHANBW
_
For best performance, the channel filter
bandwidth should be selected so that the
signal bandwidth occupies at most 80% of the
channel filter bandwidth. The channel centre
tolerance due to crystal accuracy should also
be subtracted from the signal bandwidth. The
following example illustrates this:
With the channel filter bandwidth set to 600
kHz, the signal should stay within 80% of 600
14 Demodulator, Symbol Synchronizer and Data Decision
CC2500 contains an advanced and highly
configurable demodulator. Channel filtering
and
frequency
offset
compensation
performed digitally. To generate the RSSI level
(see Section 17.3 for more information) the
signal level in the channel is estimated. Data
filtering
is
also
included
performance.
14.1
Frequency Offset Compensation
When
using
2-FSK,
GFSK,
modulation, the demodulator will compensate
for the offset between the transmitter and
receiver frequency, within certain limits, by
estimating the centre of the received data.
This value is available in the FREQEST status
register. Writing the value from FREQEST into
the
FSCTRL0.FREQOFF
synthesizer
is
automatically
according to the estimated frequency offset.
The tracking range of the algorithm is
selectable
as
fractions
of
bandwidth
with
the
FOCCFG.FOC_LIMIT
configuration register.
kHz, which is 480 kHz. Assuming 2.44 GHz
frequency and ±20 ppm frequency uncertainty
for both the transmitting device and the
receiving
uncertainty is ±40 ppm of 2.44 GHz, which is
±98 kHz. If the whole transmitted signal
oscillator
bandwidth is to be received within 480 kHz,
the transmitted signal bandwidth should be
maximum 480 kHz – 2·98 kHz, which is 284
kHz.
The CC2500 supports the following channel
filter bandwidths:
CHANBW
_
E
M
2
MDMCFG4.
CHANBW_M
Table 20: Channel Filter Bandwidths [kHz]
If the FOCCFG.FOC_BS_CS_GATE bit is set,
the offset compensator will freeze until carrier
is
sense asserts. This may be useful when the
radio is in RX for long periods with no traffic,
since the algorithm may drift to the boundaries
when trying to track noise.
for
enhanced
The tracking loop has two gain factors, which
affects the settling time and noise sensitivity of
the algorithm. FOCCFG.FOC_PRE_K sets the
gain before the sync word is detected, and
FOCCFG.FOC_POST_K selects the gain after
or
MSK
the sync word has been found.
Note that frequency offset compensation is not
supported for OOK modulation.
14.2
frequency
The bit synchronization algorithm extracts the
adjusted
clock
algorithm requires that the expected data rate
is programmed as described in Section 12 on
page 26. Re-synchronization is performed
the
channel
continuously to adjust for error in the incoming
symbol rate.
SWRS040C
device,
the
total
frequency
MDMCFG4.CHANBW_E
00
01
10
00
812
406
203
01
650
325
162
10
541
270
135
11
464
232
116
(assuming a 26 MHz crystal)
Bit Synchronization
from
the
incoming
symbols.
Page 27 of 89
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The