IC RF TXRX SNGL-CHIP LP 20-QFN

CC2500-RTR1

Manufacturer Part NumberCC2500-RTR1
DescriptionIC RF TXRX SNGL-CHIP LP 20-QFN
ManufacturerTexas Instruments
CC2500-RTR1 datasheet
 


Specifications of CC2500-RTR1

Frequency2.4GHzData Rate - Maximum500kBaud
Modulation Or Protocol2-FSK, ASK, GFSK, MSK, OOKApplicationsISM, SRD
Power - Output-30dBm ~ 10dBmSensitivity-104dBm
Voltage - Supply1.8 V ~ 3.6 VCurrent - Receiving17mA
Current - Transmitting21.5mA @ 1 dBmData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature-40°C ~ 85°C
Package / Case20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFNOperating Temperature (min)-40C
Operating Temperature (max)85COperating Temperature ClassificationIndustrial
Product Depth (mm)4mmProduct Length (mm)4mm
Operating Supply Voltage (min)1.8VOperating Supply Voltage (typ)2.5/3.3V
Operating Supply Voltage (max)3.6VFor Use With296-24121 - DEV WRLSS TOOL FOR MSP430296-23125 - TARGET BRD WIRELESS EZ430-RF2500296-23031 - DEV WRLSS TOOL FOR MSP430/CC2500296-22903 - KIT EVAL MODULE FOR CC2500296-23077 - KIT DEV FOR CC2500/CC2550
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantMemory Size-
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= 80 + j74 Ω
Z
out
To ensure optimal matching of the CC2500
differential output it is highly recommended to
28 PCB Layout Recommendations
The top layer should be used for signal
routing, and the open areas should be filled
with metallization connected to ground using
several vias.
The area under the chip is used for grounding
and shall be connected to the bottom ground
plane with several vias for good thermal
performance and sufficiently low inductance to
ground. In the CC2500EM reference designs
[4] 5 vias are placed inside the exposed die
attached pad. These vias should be “tented”
(covered with solder mask) on the component
side of the PCB to avoid migration of solder
through the vias during the solder reflow
process.
The solder paste coverage should not be
100%. If it is, out gassing may occur during the
reflow process, which may cause defects
(splattering, solder balling). Using “tented” vias
reduces the solder paste coverage below
100%.
See Figure 28 for top solder resist and top
paste masks. See Figure 30 for recommended
PCB layout for QLP 20 package.
Each decoupling capacitor should be placed
as close as possible to the supply pin it is
supposed to decouple. Each decoupling
Figure 28: Left: Top Solder Resist Mask (negative). Right: Top Paste Mask. Circles are Vias.
follow the CC2500EM reference designs [4] as
closely as possible. Gerber files for the
reference designs are available for download
from the TI website.
capacitor should be connected to the power
line by separate vias. The best routing is from
the power line to the decoupling capacitor and
then to the CC2500 supply pin. Supply power
filtering is very important.
Each decoupling capacitor ground pad should
be connected to the ground plane using a
separate via.
Direct connections between
neighboring power pins will increase noise
coupling and should be avoided unless
absolutely necessary.
The external components should ideally be as
small as possible (0402 is recommended) and
surface
mount
recommended. Please note that components
smaller than those specified may have
differing characteristics.
Precaution should be used when placing the
microcontroller
in
interfering with the RF circuitry.
A CC2500/2550DK Development Kit with a
fully
assembled
Module is available. It is strongly advised that
this reference layout is followed very closely in
order to get the best performance. The
schematic, BOM and layout Gerber files are all
available from the TI website [4].
SWRS040C
devices
are
highly
order
to
avoid
noise
CC2500EM
Evaluation
Page 51 of 89