IC RF TXRX SNGL-CHIP LP 20-QFN

CC2500-RTR1

Manufacturer Part NumberCC2500-RTR1
DescriptionIC RF TXRX SNGL-CHIP LP 20-QFN
ManufacturerTexas Instruments
CC2500-RTR1 datasheet
 


Specifications of CC2500-RTR1

Frequency2.4GHzData Rate - Maximum500kBaud
Modulation Or Protocol2-FSK, ASK, GFSK, MSK, OOKApplicationsISM, SRD
Power - Output-30dBm ~ 10dBmSensitivity-104dBm
Voltage - Supply1.8 V ~ 3.6 VCurrent - Receiving17mA
Current - Transmitting21.5mA @ 1 dBmData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature-40°C ~ 85°C
Package / Case20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFNOperating Temperature (min)-40C
Operating Temperature (max)85COperating Temperature ClassificationIndustrial
Product Depth (mm)4mmProduct Length (mm)4mm
Operating Supply Voltage (min)1.8VOperating Supply Voltage (typ)2.5/3.3V
Operating Supply Voltage (max)3.6VFor Use With296-24121 - DEV WRLSS TOOL FOR MSP430296-23125 - TARGET BRD WIRELESS EZ430-RF2500296-23031 - DEV WRLSS TOOL FOR MSP430/CC2500296-22903 - KIT EVAL MODULE FOR CC2500296-23077 - KIT DEV FOR CC2500/CC2550
Lead Free Status / RoHS StatusContains lead / RoHS non-compliantMemory Size-
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0x1A: BSCFG – Bit Synchronization Configuration
Bit
Field Name
Reset
7:6
BS_PRE_KI[1:0]
1 (01)
5:4
BS_PRE_KP[1:0]
2 (10)
3
BS_POST_KI
1
2
BS_POST_KP
1
1:0
BS_LIMIT[1:0]
0 (00)
R/W
Description
R/W
The clock recovery feedback loop integral gain to be used before a
sync word is detected (used to correct offsets in data rate):
Setting
Clock recovery loop integral gain before sync word
0 (00)
K
I
1 (01)
2K
I
2 (10)
3K
I
3 (11)
4K
I
R/W
The clock recovery feedback loop proportional gain to be used
before a sync word is detected.
Setting
Clock recovery loop proportional gain before sync word
0 (00)
K
P
1 (01)
2K
P
2 (10)
3K
P
3 (11)
4K
P
R/W
The clock recovery feedback loop integral gain to be used after a
sync word is detected.
Setting
Clock recovery loop integral gain after sync word
0
Same as BS_PRE_KI
1
K
/2
I
R/W
The clock recovery feedback loop proportional gain to be used after
a sync word is detected.
Setting
Clock recovery loop proportional gain after sync word
0
Same as BS_PRE_KP
1
K
P
R/W
The saturation point for the data rate offset compensation algorithm:
Setting
Data rate offset saturation (max data rate difference)
0 (00)
±0 (No data rate offset compensation performed)
1 (01)
±3.125% data rate offset
2 (10)
±6.25% data rate offset
3 (11)
±12.5% data rate offset
SWRS040C
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