IC RF TXRX SNGL-CHIP LP 20-QFN

CC2500RTK

Manufacturer Part NumberCC2500RTK
DescriptionIC RF TXRX SNGL-CHIP LP 20-QFN
ManufacturerTexas Instruments
CC2500RTK datasheet
 


Specifications of CC2500RTK

Frequency2.4GHzData Rate - Maximum500kBaud
Modulation Or Protocol2-FSK, ASK, GFSK, MSK, OOKApplicationsISM, SRD
Power - Output-30dBm ~ 10dBmSensitivity-104dBm
Voltage - Supply1.8 V ~ 3.6 VCurrent - Receiving17mA
Current - Transmitting21.5mA @ 1 dBmData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature-40°C ~ 85°C
Package / Case20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFNOperating Supply Voltage2.5 V, 3.3 V
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
Operating Temperature (min)-40COperating Temperature (max)85C
Operating Temperature ClassificationIndustrialProduct Depth (mm)4mm
Product Length (mm)4mmOperating Supply Voltage (min)1.8V
Operating Supply Voltage (typ)2.5/3.3VOperating Supply Voltage (max)3.6V
For Use With296-24121 - DEV WRLSS TOOL FOR MSP430296-23125 - TARGET BRD WIRELESS EZ430-RF2500296-23031 - DEV WRLSS TOOL FOR MSP430/CC2500296-22903 - KIT EVAL MODULE FOR CC2500296-23077 - KIT DEV FOR CC2500/CC2550Lead Free Status / RoHS StatusLead free / RoHS Compliant
Memory Size-Other names296-25932-5
CC2500RTK
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Page 1/96

Download datasheet (3Mb)Embed
Next
CC2500
Low-Cost Low-Power 2.4 GHz RF Transceiver
Applications
 2400-2483.5 MHz ISM/SRD band systems
 Consumer electronics
 Wireless game controllers
Product Description
The CC2500 is a low-cost 2.4 GHz transceiver
designed for very low-power wireless appli-
cations. The circuit is intended for the 2400-
2483.5 MHz ISM (Industrial, Scientific and
Medical) and SRD (Short Range Device)
frequency band.
The RF transceiver is integrated with a highly
configurable baseband modem. The modem
supports various modulation formats and has
a configurable data rate up to 500 kBaud.
CC2500 provides extensive hardware support
for packet handling, data buffering, burst
transmissions, clear channel assessment, link
quality indication, and wake-on-radio.
The main operating parameters and the 64-
byte transmit/receive FIFOs of CC2500 can be
Key Features
RF Performance
High sensitivity (–104 dBm at 2.4 kBaud,
1% packet error rate)
Low current consumption (13.3 mA in RX,
250 kBaud, input well above sensitivity
limit)
Programmable output power up to +1 dBm
Excellent receiver selectivity and blocking
performance
Programmable data rate from 1.2 to 500
kBaud
Frequency range: 2400 – 2483.5 MHz
Analog Features
OOK, 2-FSK, GFSK, and MSK supported
Suitable for frequency hopping and multi-
channel systems due to a fast settling
 Wireless audio
 Wireless keyboard and mouse
 RF enabled remote controls
controlled via an SPI interface. In a typical
system, the CC2500 will be used together with
a microcontroller and a few additional passive
components.
frequency synthesizer with 90 us settling
time
Automatic
Frequency
(AFC) can be used to align the frequency
synthesizer
to
frequency
Integrated analog temperature sensor
Digital Features
Flexible
support
systems: On-chip support for sync word
detection, address check, flexible packet
length, and automatic CRC handling
Efficient SPI interface: All registers can be
programmed with one “burst” transfer
Digital RSSI output
Programmable channel filter bandwidth
Programmable
indicator
SWRS040C
Compensation
the
received
centre
for
packet
oriented
Carrier
Sense
(CS)
Page 1 of 89

CC2500RTK Summary of contents

  • Page 1

    CC2500 Low-Cost Low-Power 2.4 GHz RF Transceiver Applications  2400-2483.5 MHz ISM/SRD band systems  Consumer electronics  Wireless game controllers Product Description The CC2500 is a low-cost 2.4 GHz transceiver designed for very low-power wireless appli- cations. The circuit ...

  • Page 2

    Programmable Preamble Quality Indicator (PQI) for improved protection against false sync word detection in random noise  Support for automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems)  Support for per-package Link Quality Indication (LQI)  Optional ...

  • Page 3

    Abbreviations Abbreviations used in this data sheet are described below. ACP Adjacent Channel Power ADC Analog to Digital Converter AFC Automatic Frequency Offset Compensation AGC Automatic Gain Control AMR Automatic Meter Reading ARIB Association of Radio Industries and Businesses BER ...

  • Page 4

    Table of Contents APPLICATIONS ...........................................................................................................................................1 PRODUCT DESCRIPTION.........................................................................................................................1 KEY FEATURES .......................................................................................................................................... ...........................................................................................................................................1 ERFORMANCE A F ..........................................................................................................................................1 NALOG EATURES D F ..........................................................................................................................................1 IGITAL EATURES ...................................................................................................................................2 OW OWER EATURES G ..........................................................................................................................................................2 ENERAL ABBREVIATIONS........................................................................................................................................3 TABLE OF CONTENTS ..............................................................................................................................4 1 ...

  • Page 5

    A M .................................................................................................................34 MPLITUDE ODULATION ECEIVED IGNAL UALIFIERS AND 17 .....................................................................................................................34 YNC ORD UALIFIER 17 REAMBLE UALITY HRESHOLD 17.3 RSSI...................................................................................................................................................34 17 (CS)..........................................................................................................................35 ARRIER ENSE 17 ...

  • Page 6

    Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Caution! ESD sensitive Precaution should be ...

  • Page 7

    Electrical Specifications 4.1 Current Consumption Tc = 25C, VDD = 3 nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Min Current consumption in power down modes Current consumption Current consumption, RX ...

  • Page 8

    Current consumption, 11.1 TX states 15.0 21.2 21.5 mA Transmit mode, –12 dBm output power mA Transmit mode, -6 dBm output power mA Transmit mode, 0 dBm output power mA Transmit mode, +1 dBm output power Table 4: Current Consumption ...

  • Page 9

    RF Receive Section Tc = 25C, VDD = 3 nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Min Typ Digital channel filter 58 bandwidth 2.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 ...

  • Page 10

    Parameter Min 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity Saturation Adjacent channel rejection Alternate channel rejection Blocking ±10 MHz offset ±20 MHz offset ...

  • Page 11

    RF Transmit Section Tc = 25C, VDD = 3 dBm if nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Parameter Min Typ Differential load 80 + j74 impedance Output power, +1 highest ...

  • Page 12

    Crystal Oscillator Tc = 25C, VDD = 3 nothing else stated. Parameter Min Typ Crystal frequency 26 26 Tolerance ±40 ESR Start-up time 150 Table 7: Crystal Oscillator Parameters 4.5 Low Power RC Oscillator Tc = 25C, ...

  • Page 13

    Frequency Synthesizer Characteristics Tc = 25C, VDD = 3 nothing else stated. All measurement results obtained using the CC2500EM reference design ([4]). Min figures are given using a 27 MHz crystal. Typ and max figures are given ...

  • Page 14

    Analog Temperature Sensor The characteristics of the analog temperature sensor at 3.0 V supply voltage are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor ...

  • Page 15

    Pin Configuration SO (GDO1) DCOUPL Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip SCLK 1 15 AVDD 2 ...

  • Page 16

    Pin # Pin Name Pin Type 1 SCLK Digital Input 2 Digital Output SO (GDO1) 3 GDO2 Digital Output 4 DVDD Power (Digital) 5 DCOUPL Power (Digital) 6 GDO0 Digital I/O (ATEST) 7 Digital Input CSn 8 XOSC_Q1 Analog I/O ...

  • Page 17

    Circuit Description LNA RF_P 0 RF_N OSC BIAS RBIAS Figure 2: CC2500 Simplified Block Diagram A simplified block diagram of CC2500 is shown in Figure 2. CC2500 features a low-IF receiver. The received RF signal is ...

  • Page 18

    RF signal on CC2500 to a single-ended RF signal. C121 and C131 are needed for DC blocking. Together with an appropriate LC network, the balun components also impedance to match a 50  antenna (or ...

  • Page 19

    Component C51 C81 C101 C121 C122 C123 C124 C131 C132 L121 L122 L131 R171 XTAL Table 15: Bill Of Materials for the Application Circuit Measurements have been performed with multi-layer inductors from other manufacturers (e.g. Würth) and the measurement results ...

  • Page 20

    Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.5mA. Used for calibrating frequency synthesizer upfront (entering receive or transmit mode can Manual freq. then be done quicker). synth. calibration Transitional state. Typ. current consumption: 7.4mA. ...

  • Page 21

    Figure 6: SmartRF 10 4-wire Serial Configuration and Data Interface CC2500 is configured via a simple 4-wire SPI- compatible interface (SI, SO, SCLK and CSn) where CC2500 is the slave. This interface is also used to read and write buffered ...

  • Page 22

    Figure 7: Configuration Register Write and Read Operations Parameter Description f SCLK frequency SCLK 100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access). SCLK frequency, ...

  • Page 23

    The RX state will be active when the chip is in receive mode. Likewise active when the chip is transmitting. The last four bits (3:0) in ...

  • Page 24

    MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt probability of any single read from TXBYTES being corrupt, assuming the maximum data ...

  • Page 25

    When using OOK modulation the first two entries into this table are used (index 0 and index 1). Since the PATABLE is an 8-byte table, the table is written and read from the lowest setting (0) to the highest ...

  • Page 26

    The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on the GDO0 pin with an external ADC, the temperature can be Specifications for the temperature sensor are found in Section 4.7 on ...

  • Page 27

    Receiver Channel Filter Bandwidth In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth, which scales with the crystal frequency. The following formula ...

  • Page 28

    Byte Synchronization Byte synchronization is achieved continuous sync word search. The sync word bit configurable field (can be repeated to get a 32 bit) that is automatically inserted at the start of the packet by the ...

  • Page 29

    Data Whitening From a radio perspective, the ideal over the air data are random and DC free. This results in the smoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniform operation ...

  • Page 30

    The preamble pattern is sequence of ones and zeros (101010101…). The minimum length of the preamble is programmable. When enabling modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send ...

  • Page 31

    Pre-program the PKTLEN mod(600,256)=88.  Transmit at least 345 bytes, for example by filling the 64-byte TX FIFO six times (384 bytes transmitted). Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 ...

  • Page 32

    Refer also to the CC2500 Errata Notes [1]. 15.4.1 PKTCTRL0.CC2400_EN=0 If PKTCTRL0.CC2400_EN possible to read back the CRC status in 2 different ways: 1) Set PKTCTRL1.APPEND_STATUS=1 and read the CRC_OK flag in the MSB of the second ...

  • Page 33

    CRC status, link quality indication and RSSI value. 15.7 Packet Handling in Firmware When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been received/transmitted. Additionally, for packets longer ...

  • Page 34

    The fraction of a symbol period used to change the phase can be modified with the setting. DEVIATN.DEVIATION_M equivalent to changing the shaping of the symbol. The MSK modulation format implemented in CC2500 inverts the sync word and data compared ...

  • Page 35

    The RSSI value read from the RSSI status register is a 2’s complement number. The following procedure can be used to convert the RSSI reading to an absolute power ...

  • Page 36

    IOCFGx.GDOx_CFG=14 and in the status register bit PKTSTATUS.CS. Other uses of Carrier Sense include the TX-if- CCA function (see Section 17.5 on page 37) and the optional fast RX termination (see Section 19.7 on page 43). CS can be used ...

  • Page 37

    Clear Channel Assessment (CCA) The Clear Channel Assessment CCA) is used to indicate if the current channel is free or busy. The current CCA state is viewable on any of the GDO pins by setting IOCFGx.GDOx_ CFG=0x09. MCSM1.CCA_MODE selects ...

  • Page 38

    In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart. ...

  • Page 39

    Radio Control CAL_ COMPLETE MANCAL 3,4,5 FSTXON 18 STX TXOFF _ MODE=01 STX | RXOFF _ MODE = 10 TX TXOFF _ MODE = 10 19,20 SRX | TXOFF _ MODE = 11 TXOFF _ MODE = 00 TXFIFO ...

  • Page 40

    Automatic POR A power-on reset circuit is included in the CC2500 . The minimum requirements stated in Section 4.9 must be followed for the power-on reset to function properly. The internal power- up sequence is completed when CHIP_RDYn goes ...

  • Page 41

    IDLE state. When wake on radio is enabled, the WOR module will control the voltage regulator as described in Section 19.5. 19.4 Active Modes CC2500 has two active modes: receive and transmit. These ...

  • Page 42

    Event 1 follows Event 0 after a programmed timeout. The time between two consecutive Event 0 is programmed with a mantissa value given by WOREVT1.EVENT0 and WOREVT0.EVENT0, and an exponent value WORCTRL.WOR_RES. The equation is: 750   t EVENT ...

  • Page 43

    RX Termination Timer CC2500 has optional functions for automatic termination of RX after a programmable time. The main use for this functionality is wake-on- radio (WOR), but it may be useful for other applications. The termination timer starts when ...

  • Page 44

    Read RXBYTES.NUM_RXBYTES repeatedly at a rate guaranteed least twice that of which RF bytes are received until the same value is returned n. twice; store value < bytes remaining in ...

  • Page 45

    The desired channel number is programmed with the 8-bit channel number register,  f   XOSC f FREQ carrier 16 2 With a 26 ...

  • Page 46

    Voltage Regulators CC2500 contains several on-chip linear voltage regulators, which generate the supply voltage needed by low-voltage modules. voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must ...

  • Page 47

    Figure 21: PA_POWER and PATABLE Default power setting 0xC6 Table 30: Output Power and Current Consumption for Default PATABLE Setting Output Power, Typical, +25°C, 3.0 V [dBm] (–55 or less) –30 –28 –26 –24 –22 –20 –18 –16 –14 –12 ...

  • Page 48

    Selectivity Figure 22 to Figure 26 show the typical selectivity performance (adjacent and alternate rejection). -1 -0.8 Figure 22: Typical Selectivity at 2.4 kBaud. IF Frequency is 273.9 kHz. -1 -0.8 Figure 23: Typical Selectivity at 10 kBaud. IF ...

  • Page 49

    Figure 24: Typical Selectivity at 250 kBaud. IF Frequency is 177.7 kHz. MDMCFG2.DEM_DCFILT_OFF Figure 25: Typical Selectivity at 250 kBaud. IF Frequency is 457 kHz. MDMCFG2.DEM_DCFILT_OFF Figure 26: Typical Selectivity at ...

  • Page 50

    Crystal Oscillator A crystal in the frequency range 26-27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C81 and C101) for the ...

  • Page 51

    Z out To ensure optimal matching of the CC2500 differential output it is highly recommended to 28 PCB Layout Recommendations The top layer should be used for signal routing, and the open areas should be ...

  • Page 52

    General Purpose / Test Output Control Pins The three digital output pins GDO0, GDO1 and GDO2 are general control pins configured with IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG respectively. Table 33 shows the different signals that can be monitored on the ...

  • Page 53

    GDOx _CFG[5:0]] Description Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-asserts when RX 0 (0x00) FIFO is drained below the same threshold. Associated to the RX FIFO: Asserts when ...

  • Page 54

    Asynchronous and Synchronous Serial Operation Several features and modes of operation have been included in the CC2500 to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems recommended to use ...

  • Page 55

    Frequency Hopping Channel Systems The 2.400 – 2.4835 GHz band is shared by many systems both in industrial, office and home environments. It recommended to use frequency hopping spread spectrum (FHSS multi-channel protocol because the frequency diversity ...

  • Page 56

    Crystal Drift Compensation The CC2500 has a very fine frequency resolution (see Table 9). This feature can be used to compensate for frequency offset and drift. The frequency offset between an ‘external’ transmitter and the receiver is measured in ...

  • Page 57

    Configuration Registers The configuration of CC2500 is done by programming 8-bit registers. The optimum configuration data based on selected system parameters are most easily found by using the  SmartRF Studio software [5]. Complete descriptions of the registers are ...

  • Page 58

    Address Register Description 0x00 IOCFG2 GDO2 output pin configuration GDO1 output pin configuration 0x01 IOCFG1 0x02 IOCFG0 GDO0 output pin configuration 0x03 FIFOTHR RX FIFO and TX FIFO thresholds 0x04 SYNC1 Sync word, high byte 0x05 SYNC0 Sync word, low ...

  • Page 59

    Address Register 0x30 (0xF0) PARTNUM 0x31 (0xF1) VERSION 0x32 (0xF2) FREQEST 0x33 (0xF3) LQI 0x34 (0xF4) RSSI 0x35 (0xF5) MARCSTATE 0x36 (0xF6) WORTIME1 0x37 (0xF7) WORTIME0 0x38 (0xF8) PKTSTATUS 0x39 (0xF9) VCO_VC_DAC 0x3A (0xFA) TXBYTES 0x3B (0xFB) RXBYTES 0x3C (0xFC) ...

  • Page 60

    Write Single byte Burst +0x00 +0x40 0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNC0 0x06 PKTLEN 0x07 PKTCTRL1 0x08 PKTCTRL0 0x09 ADDR 0x0A CHANNR 0x0B FSCTRL1 0x0C FSCTRL0 0x0D FREQ2 0x0E FREQ1 0x0F FREQ0 0x10 MDMCFG4 ...

  • Page 61

    Configuration Register Details – Registers with Preserved Values in SLEEP State 0x00: IOCFG2 – GDO2 Output Pin Configuration Bit Field Name 7 Reserved 6 GDO2_INV 5:0 GDO2_CFG[5:0] 0x01: IOCFG1 – GDO1 Output Pin Configuration Bit Field Name 7 GDO_DS ...

  • Page 62

    FIFOTHR – RX FIFO and TX FIFO Thresholds Bit Field Name 7:4 Reserved 3:0 FIFO_THR[3:0] 0x04: SYNC1 – Sync Word, High Byte Bit Field Name 7:0 SYNC[15:8] 0x05: SYNC0 – Sync Word, Low Byte Bit Field Name 7:0 SYNC[7:0] ...

  • Page 63

    PKTCTRL1 – Packet Automation Control Bit Field Name Reset 7:5 PQT[2:0] 0 (000) 4 Reserved 0 3 CRC_AUTOFLUSH 0 2 APPEND_STATUS 1 1:0 ADR_CHK[1:0] 0 (00) R/W Description R/W Preamble quality estimator threshold. The preamble quality estimator increases an ...

  • Page 64

    PKTCTRL0 – Packet Automation Control Bit Field Name 7 Reserved 6 WHITE_DATA 5:4 PKT_FORMAT[1:0] 3 CC2400_EN 2 CRC_EN 1:0 LENGTH_CONFIG[1:0] Bit Field Name 7:0 DEVICE_ADDR[7:0] 0x0A: CHANNR – Channel Number Bit Field Name Reset 7:0 CHAN[7:0] 0 (0x00) Reset ...

  • Page 65

    FSCTRL1 – Frequency Synthesizer Control Bit Field Name Reset 7:5 Reserved 4:0 FREQ_IF[4:0] 15 (0x0F) 0x0C: FSCTRL0 – Frequency Synthesizer Control Bit Field Name 7:0 FREQOFF[7:0] 0x0D: FREQ2 – Frequency Control Word, High Byte Bit Field Name Reset 7:6 ...

  • Page 66

    MDMCFG4 – Modem Configuration Bit Field Name Reset 7:6 CHANBW_E[1:0] 2 (10) 5:4 CHANBW_M[1:0] 0 (00) 3:0 DRATE_E[3:0] 12 (1100) 0x11: MDMCFG3 – Modem Configuration Bit Field Name Reset 7:0 DRATE_M[7:0] 34 (0x22) R/W Description R/W R/W Sets the ...

  • Page 67

    MDMCFG2 – Modem Configuration Bit Field Name 7 DEM_DCFILT_OFF 6:4 MOD_FORMAT[2:0] 3 MANCHESTER_EN 2:0 SYNC_MODE[2:0] Reset R/W Description 0 R/W Disable digital DC blocking filter before demodulator Enable (better sensitivity Disable (current optimized). Only for ...

  • Page 68

    MDMCFG1 – Modem Configuration Bit Field Name Reset 7 FEC_EN 0 6:4 NUM_PREAMBLE[2:0] 2 (010) 3:2 Reserved 1:0 CHANSPC_E[1:0] 2 (10) 0x14: MDMCFG0 – Modem Configuration Bit Field Name Reset 7:0 CHANSPC_M[7:0] 248 (0xF8) R/W Description R/W Enable Forward ...

  • Page 69

    DEVIATN – Modem Deviation Setting Bit Field Name Reset 7 Reserved 6:4 DEVIATION_E[2:0] 4 (100) 3 Reserved 2:0 DEVIATION_M[2:0] 7 (111) R/W Description R0 R/W Deviation exponent R0 R/W When MSK modulation is enabled: Sets fraction of symbol period ...

  • Page 70

    MCSM2 – Main Radio Control State Machine Configuration Bit Field Name 7:5 Reserved 4 RX_TIME_RSSI 3 RX_TIME_QUAL 2:0 RX_TIME[2:0] The RX timeout in µs is given by EVENT0·C(RX_TIME, WOR_RES) ·26/X, where C is given by the table below and ...

  • Page 71

    MCSM1 – Main Radio Control State Machine Configuration Bit Field Name 7:6 Reserved 5:4 CCA_MODE[1:0] 3:2 RXOFF_MODE[1:0] 1:0 TXOFF_MODE[1:0] Reset R/W Description R0 3 (11) R/W Selects CCA_MODE; Reflected in CCA signal Setting Clear channel indication 0 (00) Always ...

  • Page 72

    MCSM0 – Main Radio Control State Machine Configuration Bit Field Name Reset 7:6 Reserved 5:4 FS_AUTOCAL[1:0] 0 (00) 3:2 PO_TIMEOUT 1 (01) 1 PIN_CTRL_EN 0 0 XOSC_FORCE_ON 0 R/W Description R0 R/W Automatically calibrate when going ...

  • Page 73

    FOCCFG – Frequency Offset Compensation Configuration Bit Field Name 7:6 Reserved 5 FOC_BS_CS_GATE 4:3 FOC_PRE_K[1:0] 2 FOC_POST_K 1:0 FOC_LIMIT[1:0] Reset R/W Description R0 1 R/W If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops ...

  • Page 74

    BSCFG – Bit Synchronization Configuration Bit Field Name Reset 7:6 BS_PRE_KI[1:0] 1 (01) 5:4 BS_PRE_KP[1:0] 2 (10) 3 BS_POST_KI 1 2 BS_POST_KP 1 1:0 BS_LIMIT[1:0] 0 (00) R/W Description R/W The clock recovery feedback loop integral gain to be ...

  • Page 75

    Bit Field Name Reset 7:6 MAX_DVGA_GAIN[1:0] 0 (00) 5:3 MAX_LNA_GAIN[2:0] 0 (000) 2:0 MAGN_TARGET[2:0] 3 (011) 0x1B: AGCCTRL2 – AGC Control R/W Description R/W Reduces the maximum allowable DVGA gain. Setting Allowable DVGA settings 0 (00) All gain settings can ...

  • Page 76

    Bit Field Name 7 Reserved 6 AGC_LNA_PRIORITY 5:4 CARRIER_SENSE_REL_THR[1:0] 3:0 CARRIER_SENSE_ABS_THR[3:0] 0x1C: AGCCTRL1 – AGC Control Reset R/W Description R0 1 R/W Selects between two different strategies for LNA and LNA2 gain adjustment. When 1, the LNA gain is decreased ...

  • Page 77

    Bit Field Name 7:6 HYST_LEVEL[1:0] 5:4 WAIT_TIME[1:0] 3:2 AGC_FREEZE[1:0] 1:0 FILTER_LENGTH[1:0] 0x1E: WOREVT1 – High Byte Event0 Timeout Bit Field Name Reset 7:0 EVENT0[15:8] 135 (0x87) 0x1D: AGCCTRL0 – AGC Control Reset R/W Description 2 (10) R/W Sets the level ...

  • Page 78

    WOREVT0 – Low Byte Event0 Timeout Bit Field Name Reset 7:0 EVENT0[7:0] 107 (0x6B) 0x20: WORCTRL – Wake On Radio Control Bit Field Name Reset 7 RC_PD 1 6:4 EVENT1[2:0] 7 (111) 3 RC_CAL 1 2 Reserved 1:0 WOR_RES[1:0] ...

  • Page 79

    FREND0 – Front End TX configuration Bit Field Name 7:6 Reserved 5:4 LODIV_BUF_CURRENT_TX[1:0] 3 Reserved 2:0 PA_POWER[2:0] 0x23: FSCAL3 – Frequency Synthesizer Calibration Bit Field Name 7:6 FSCAL3[7:6] 5:4 CHP_CURR_CAL_EN[1:0] 3:0 FSCAL3[3:0] 0x24: FSCAL2 – Frequency Synthesizer Calibration Bit ...

  • Page 80

    FSCAL1 – Frequency Synthesizer Calibration Bit Field Name 7:6 Reserved 5:0 FSCAL1[5:0] 0x26: FSCAL0 – Frequency Synthesizer Calibration Bit Field Name 7 Reserved 6:0 FSCAL0[6:0] 0x27: RCCTRL1 – RC Oscillator Configuration Bit Field Name 7 Reserved 6:0 RCCTRL1[6:0] 0x28: ...

  • Page 81

    Bit Field Name Reset 7:0 AGCTEST[7:0] 63 (0x3F) 0x2C: TEST2 – Various Test Settings Bit Field Name Reset 7:0 TEST2[7:0] 136 (0x88) 0x2D: TEST1 – Various Test Settings Bit Field Name Reset 7:0 TEST1[7:0] 49 (0x31) 0x2E: TEST0 – Various ...

  • Page 82

    LQI – Demodulator Estimate for Link Quality Bit Field Name Reset 7 CRC_OK 6:0 LQI_EST[6:0] 0x34 (0xF4): RSSI – Received Signal Strength Indication Bit Field Name Reset 7:0 RSSI 0x35 (0xF5): MARCSTATE – Main Radio Control State Machine ...

  • Page 83

    WORTIME1 – High Byte of WOR Time Bit Field Name Reset 7:0 TIME[15:8] 0x37 (0xF7): WORTIME0 – Low Byte of WOR Time Bit Field Name Reset 7:0 TIME[7:0] 0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status ...

  • Page 84

    RXBYTES – Underflow and Number of Bytes Bit Field Name Reset 7 RXFIFO_OVERFLOW 6:0 NUM_RXBYTES 0x3C (0xFC): RCCTRL1_STATUS – Last RC Oscillator Calibration Result Bit Field Name Reset 7 Reserved 6:0 RCCTRL1_STATUS[6:0] 0x3D (0xFC): RCCTRL0_STATUS – Last RC ...

  • Page 85

    Package Description (QFN 20) 33.1 Recommended PCB Layout for Package (QFN 20) Figure 30: Recommended PCB Layout for QFN 20 Package Note: The figure is an illustration only and not to scale. There are five 10 mil diameter via ...

  • Page 86

    ... Ordering Information Orderable Status Package Device (1) Type CC2500RTKR Active QFN CC2500RTK Active QFN Orderable Evaluation Module CC2500-CC2550DK CC2500EMK 35 References [1] CC2500 Errata Notes (swrz002.pdf) [2] AN032 2.4 GHz Regulations (swra060.pdf) [3] AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf) [4] CC2500EM Reference Design 1.0 (swrr016.zip) Package Pins Package ...

  • Page 87

    SmartRF Studio (swrc046.zip) [6] CC1100 CC2500 Examples Libraries (swrc021.zip) [7] CC1100/CC1150DK & CC2500/CC2550DK Development Kit Examples & Libraries User Manual (swru109.pdf) [8] CC25XX Folded Dipole Reference Design (swrc065.zip) [9] DN004 Folded Dipole Antenna for CCC25xx (swra118.pdf) SWRS040C Page ...

  • Page 88

    General Information 36.1 Document History Revision Date Description/Changes SWRS040C 2008-05-04 Updated package and ordering information. SWRS040B 2007-05-09 kbps replaced by kBaud throughout the document. Some of the sections have been re-written to be easier to read without having any ...

  • Page 89

    Revision Date Description/Changes 2006-06-28 Added figures to table on SPI interface timing requirements. 1.2 Added information about SPI read. SWRS040A Updates to text and included new figure in section on arbitrary length configuration. Updates to section on CRC check. Added ...

  • Page 90

    ... CC2500RTK ACTIVE CC2500RTKG3 ACTIVE CC2500RTKR ACTIVE CC2500RTKRG3 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

  • Page 91

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing CC2500RTKR VQFN RTK PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 20 3000 330.0 12.4 4.3 Pack Materials-Page 1 8-Dec-2009 Pin1 (mm) (mm) (mm) (mm) Quadrant 4.3 1.5 8 ...

  • Page 92

    ... Device Package Type CC2500RTKR VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RTK 20 3000 Pack Materials-Page 2 8-Dec-2009 Width (mm) Height (mm) 378.0 70.0 346.0 ...

  • Page 93

    ...

  • Page 94

    ...

  • Page 95

    ...

  • Page 96

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...