CC1010-RTR1

... The together with a few external passive components constitutes powerful embedded system with wireless communication capabilities. CC1010 is based on Chipcon’s SmartRF technology in 0.35 µm CMOS. Key Features • 300-1000 MHz RF Transceiver • Very low current consumption (9 RX) • High sensitivity (typically -107 dBm) • ...

Table Of Contents 1. FEATURES..................................................................................................................... 4 2. ABSOLUTE MAXIMUM RATINGS ................................................................................ 5 3. RECOMMENDED OPERATING CONDITIONS............................................................. CHARACTERISTICS ............................................................................................... 6 5. ELECTRICAL SPECIFICATIONS.................................................................................. 7 6. ADC ................................................................................................................................ SECTION, GENERAL .............................................................................................. TRANSMIT SECTION ...

D EMODULATION AND DATA DECISION 17.10 S YNCHRONIZATION AND PREAMBLE DETECTION 17.11 R ECEIVER SENSITIVITY VERSUS DATA RATE AND FREQUENCY SEPARATION 17.12 F REQUENCY PROGRAMMING 17. ................................................................................................... 110 OCK NDICATION 17. ECOMMENDED ETTINGS FOR 17.15 ...

Features Fully Integrated UHF RF Transceiver • Programmable frequency in the range 300 – 1000 MHz • High sensitivity (typically -107 dBm at 2.4 kBaud) • Programmable output power –20 to +10 dBm • Very low current consumption (RX: ...

Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Parameter Min. Supply voltage, VDD -0.3 ...

... DC Characteristics CC1010 The DC Characteristics 25°C, VDD = 3 nothing else stated Digital Inputs/Outputs Logic "0" input voltage Logic "1" input voltage Logic "0" output voltage Logic "1" output voltage Logic "0" output voltage Logic "1" output voltage Logic "0" input current Logic "1" input current ...

... Electrical Specifications Tc = 25°C, VDD = 3 nothing else stated All electrical specifications are measured on Chipcon’s CC1010EM reference design. Parameter Power on reset (POR) voltage Brown out voltage RTC start-up time Current consumption MCU, Active mode Current consumption MCU, Idle mode Current consumption, Power ...

ADC Parameter Min. Number of bits Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Offset Total Harmonic Distortion (THD) SINAD Internal reference tolerance Conversion time 44 Clock frequency 32 External reference voltage Input voltage section, general Parameter Min. ...

RF transmit section Parameter Min. Binary FSK frequency 0 separation Output power -20 433 / 868 MHz RF output impedance 433 / 868 MHz Harmonics nd 2 harmonic, 433 / 868 MHz rd 3 harmonic, 433 / 868 MHz ...

RF receive section Parameter Min. Receiver Sensitivity, 433 / 868 MHz System noise bandwidth Cascaded noise figure 433/868 MHz Saturation (maximum input 10 level) Input IP3 Blocking LO leakage Input impedance Turn on time 11 Table 8. RF receive ...

IF section Parameter Min. Intermediate frequency (IF) 433/868 MHz IF bandwidth (noise bandwidth) RSSI dynamic range -105 RSSI 3-dB bandwidth RSSI accuracy RSSI linearity Typ. Max. Unit 150/ kHz 130 10.7 MHz 175 kHz -60 dBm 260 kHz ± ...

Frequency synthesizer section Parameter Min. Crystal Oscillator Frequency 3 Crystal frequency accuracy requirement Crystal operation Crystal load capacitance Crystal oscillator start-up time Output signal phase noise PLL lock time ( turn time) PLL ...

Pin Configuration AVDD 1 AVDD 2 AGND 3 RF_IN 4 RF_OUT 5 AVDD 6 AGND 7 AGND 8 AGND ...

Pin Pin name Alternate # function 13 CHP_OUT - 14 R_BIAS - 15 AVDD - 16 AGND - 17 AGND - 18 XOSC_Q1 - 19 XOSC_Q2 - 20 XOSC32_Q - 2 21 XOSC32_Q - 1 22 AGND - 23 DGND ...

Pin Pin name Alternate # function 51 P0.2 MI (I) SO ( PROG 59 - RESET 60 DVDD - 61 ...

RBIAS Current output from internal band gap cell bias generator. A precision resistor (82 kΩ, ±1%) should be connected between this pin and ground to set the correct bias current level. XOSC_Q1, XOSC_Q2 These are the main oscillator connection pins. ...

Pins P3.0 and P3.1 can be configured to become the RXD0 and TXD0 respectively, of UART 0. Pins P3.2 and P3.3 are connected to the external interrupt inputs INT0 and INT1 , respectively, and can cause interrupts if the corresponding ...

... SPI AD0 ADC AD1 AD2 MUX (RSSI/IF) IF MIXER RF_IN LNA RF_OUT PA VCO L1 L2 VCO inductor Figure 2. CC1010 Block Diagram DES Module FLASH Programming DMA 8051 core Special Function Registers (SFRs) RF Transceiver RSSI CODEC, Bit synchronizer, IF stage MODEM Serializer/Deserializer :N.n LPF CHP ...

... POR CC1010 module, as described in the Power On : Reset (Brown-Out Detection) section at page 62. • Brown-out detection reset. The POR CC1010 . will also detect low supply voltage and generate a reset. input is • Watchdog timer reset. The watchdog timer can generate a reset, described in the section on page 63. • ...

... CC1010 has MOV commands, but uses the method described in the 8051 Flash Programming section on page 42. CC1010 also provides a possibility to stretch the access cycle to external RAM, through CKCON.MD(2:0) (see page 55). The default value for CKCON.MD is "001" recommended to set CKCON.MD to "000" ...

Internal RAM / SFR 0xFF Special Function Registers (SFR), accessible through Direct Addressing 0x7F Internal RAM Accessible through Direct and Indirect Addressing 0x00 DPL0 (0x82) - Data Pointer 0, low byte Bit Name R/W 7:0 DPL0(7:0) R/W DPH0 (0x83) - ...

... FREQ_1A FREQ_2A CRPCON CRPKEY RADRH CRPINI4 - - CRPINI0 T3PRE T2 SPSR P0DIR - - - ADCON ADDATL TL0 TL1 TH0 DPH0 DPL1 CC1010 Table 11 SFR Overview SWRS047A are used are used 6/E 7/F TEST4 TEST5 TEST6 FSHAPE3 FSHAPE2 FSHAPE1 RTCON FREND TESTMUX CAL PRESCALER RESERVED FLTIM - - ...

... CPU Registers CC1010 provides 4 register banks of 8 registers each. These register banks are mapped in the the internal data memory (see the Memory section on page 33) at addresses 0x00 - 0x07, 0x08 - 0x0F, 0x10 - 0x17 and 0x18 - 0x1F. Each register bank contains the 8 8-bit registers R0 through R7 ...

SP (0x81) - Stack Pointer Bit Name R/W 7:0 SP(7:0) R/W 15.5 Instruction Set Summary The 8051 instruction set is summarised in Table 12 below. All mnemonics are Copyright © Intel Corporation 1980. One non-standard 8051 instruction, TRAP, with opcode ...

Mnemonic Description SUBB A, @Ri Subtract data memory from A with borrow Subtract immediate from A with SUBB A, #data borrow INC A Increment A Increment register INC Rn INC direct Increment direct byte Increment data memory INC @Ri DEC ...

Mnemonic Description MOV A, @Ri Move data memory to A Move immediate to A MOV A, #data MOV Rn, A Move A to register Move direct byte to register MOV Rn, direct MOV Rn, #data Move immediate to register Move ...

Mnemonic Description Absolute call to subroutine ACALL addr 11 LCALL addr 16 Long call to subroutine Return from subroutine RET RETI Return from interrupt Absolute jump unconditional AJMP addr 11 LJMP addr 16 Long jump unconditional Short jump (relative address) ...

... IE.ET1 TCON.TF1 IE.ES0 SCON0.TI_0 SCON0.RI_0 IE.ES1 SCON1.TI_1 SCON1.TI_1 EIE.RFIE EXIF.RFIF EIE.ET2 EXIF.TF2 EIE.ADIE EXIF.ADIF and and ADCON2. ADCON2. ADCIE ADCIF EIE.ADIE EXIF.ADIF and and CRPCON. CRPCON. CRPIE CRPIF EIE.ET3 EXIF.TF3 EIE.RTCIE EICON.RTCIF CC1010 returns CC1010 completes one Page 28 of 146 ...

IE (0xA8) - Interrupt Enable Register Bit Name R R/W 6 ES1 R R/W 4 R/W ES0 3 ET1 R/W 2 EX1 R/W 1 ET0 R/W 0 EX0 R/W EIE (0xE8) - Extended Interrupt Enable Register ...

EICON (0xD8) - Extended Interrupt Control Bit Name R/W Reset value 7 SMOD1 R FDIE R FDIF R RTCIF R ...

Interrupt Priority Interrupts are prioritised in two stages: Interrupt level and natural priority. The interrupt level (low, high or highest) takes precedence over the natural priority. The Flash / Debug Interrupt, if enabled, always has the highest priority and ...

... CC1010 The when an external interrupt pin is activated, but the external interrupt pins cannot wake CC1010 the from Power-Down mode. The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Typically the total parasitic capacitance is 3-5pF ...

XOSC_Q1 XTAL XTAL C181 Figure 4. Crystal oscillator circuit Item C171 15 pF C181 15 pF Table 14. Crystal oscillator component values XOSC_Q2 C171 SWRS047A Page ...

... Turn the power off and on. The Power On Reset module should then be enabled external reset signal All should be applied during power up. More information about minimising the power consumption of the CC1010 can be found in Application Note AN017 Low Power Systems Using The CC1010. SWRS047A any reset condition ...

Mode Core Peripherals Main osc. Main osc. Active RTC osc. RTC osc. (32 kHz) (32 kHz) Stopped Main osc. Idle Stopped RTC osc. (32 kHz) ADC Off Stopped ADC On (32 kHz) Power-Down Stopped Stopped Note 1: Flash duty-cycle reduction ...

... The oscillator is powered The oscillator is powered down (default after reset) Select different Clock Modes for the 8051 and its peripherals Clock Mode 0 is selected (default after reset Clock Mode 1 is selected SWRS047A STOP bit CC1010 bit places Page 36 of 146 ...

... Flash Program Memory CC1010 has 32 kBytes of on-chip Flash program memory divided into 256 pages of 128 bytes each. It can be programmed / erased through a serial SPI interface or page-by-page from the 8051 as described in the following sections. The endurance for the Flash program memory is typically 20.000 erase / write cycles ...

When a read instruction returns anything other than $FF all flash write operations have finished. Instruction Byte 1 Byte 2 Programming 1010 1100 0101 0011 Enable Set Flash 1010 1100 0101 1101 ...

... Table 17. SPI Flash Programming Timing Parameters 15.12.2 Programming Enable Programming Enable is always the first instruction to be sent. It must be sent to synchronise the data flow and enable CC1010 to receive further instructions. Synchronisation is achieved when byte 2 of the instruction (0x53) is echoed back from the SPI interface as byte 3. If synchronisation is not achieved, byte 3 will return all zeros ...

Write Program Memory Page The Write Program Memory instruction writes the 128 bytes buffered through the Load Program Memory Page instructions to Flash memory. After issuing this command, wait 5.4 ms for it to complete also possible ...

... Initialisation. CC1010 is now ready to be programmed, as described in the next section. SWRS047A Value Meaing 0x7F JEDEC manufacturer 0x7F ID, identifies Chipcon AS as the 0x7F manufacturer. 0x9E 0x95 Identifies 32 kBytes of Flash memory CC1010 0x00 Identifies between the last XOSC Program Memory Page 41 of 146 ...

Programming the Flash Memory After the initialisation is completed, SPI programming can be performed as follows: • Device identity can be verified using the Read Signature Byte instruction. • Perform Chip Erase. • Load one page into the buffer ...

FLADR (0xAE) - Flash Write Address Register Bit Name R/W Reset value 7:0 FLADR(7:0) R/W 0x00 FLCON (0xAF) - Flash Write Control Register Bit Name R/W Reset value 6:5 FLASH_LP R/W 00 (1:0) 4 WRFLASH R/W ...

The Flash module can be set into different power modes using the control bits introduced FLCON.FLASH_LP(1:0) the previous section. After reset, the Flash module is always active, drawing a static approximately 2.5 mA (at 15.15 In Circuit Debugging In order ...

... Reset value Description 0x00 is a read-only status word, which CHIP_TYPE gives the type number of the chip. CC1010 000000 : 000001 - 111111 : Reserved for future use 0x01 is a read only status word, which gives CHIP_REV the chip revision number of the chip. Current chip ...

SWRS047A Page 46 of 146 ...

... I/O pins in the port are configured as outputs the |=, &= and ^= operators should be used to set, clear and toggle pins respectively. CC1010 The ports standard 8051-port in the following ways: • No pull-ups / pull-downs on pins • ...

Port Available pins Normal operation P0.0 SCK , SPI Serial Clock output P0 SPI Master Output P0 , SPI Master Input P0.2 MI P0.3 - P1.0 - P1.1 - P1 P1.4 P1.5 - ...

Alternate function enable Alternate function static direction or PxDIR.y PxDIR.y Alternate data Read output register enable Internal Data Bus Read Pin Enable P0 (0x80) - Port 0 Data Register Bit Name R/W Reset value ...

P2 (0xA0) - Port 2 Data Register Bit Name R/W Reset value 7 P2_7 R P2_6 R P2_5 R R/W 1 P2_4 3 P2_3 R R/W 1 P2_2 1 P2_1 R/W 1 ...

P2DIR (0xA6) - Port 2 Direction Register Bit Name R/W Reset value 7 P2DIR_7 R P2DIR_6 R P2DIR_5 R R/W 1 P2DIR_4 3 P2DIR_3 R R/W 1 P2DIR_2 1 P2DIR_1 R/W 1 ...

... Timer 0 / Timer 1 CC1010 contains two standard timers/counters (Timer 0 and Timer 1) which can operate as either a timer with a clock rate based on the system clock (as defined by the current clock mode event counter clocked by the T0 (P3.4 for Timer (P3.5 for Timer 1) inputs. TL0 (0x8A) - Timer / Counter 0 Low byte counter value ...

TMOD (0x89) - Timer / Counter 0 and 1 Mode register Bit Name R/W Reset value 7 GATE1 R R M1.1 R M1.0 R GATE0 R R/W ...

TCON (0x88) - Timer / Counter 0 and 1 control register Bit Name R/W Reset value 7 TF1 R R/W 0 TR1 5 TF0 R TR0 R IE1 R/ IT1 R/W 0 ...

CKCON (0x8E) - Timer Clock rate Control Register Bit Name R/W Reset value R/W 0 T1M 3 T0M R/W 0 2:0 R/W 001 MD(2:0) 16.2.2 Mode 0 ...

Divide by 12 System Clk Divide TR0 / TR1 GATE0 / GATE1 INT0 / INT1 Figure 8. Mode 0 and Mode 1 operation for Timer / Counter 16.2.3 Mode 1 Mode 1 ...

Divide by 12 System Clk Divide TR0 / TR1 GATE0 / GATE1 INT0 / INT1 Figure 9. Mode 2 operation for Timer / Counter 16.2.5 Mode 3 In Mode 3, which is ...

TR1 Divide T0M µ C Clk 0 1 Divide TR0 GATE0 INT0 Figure 10. Mode 3 operation for Timer / Counter 0 Clock TH0 Timer 1 interrupt TF1 request TL0 Clock Timer ...

... Timer with PWM CC1010 also features two timers with pulse width modulation (PWM) outputs. Each timer can generate interrupts, described in the Interrupts section on page 28. The timers are individually set in one of two modes, timer mode or PWM mode. This is controlled through the bits M2 and ...

Clk System Divide Clock by 255 (or T3) TR2 (or TR3) Figure 11. Timer Mode operation for Timer 2 / Timer 3 T2PRE (0xAA) - Timer 2 Prescaler Control Bit Name R/W Reset ...

The PWM “high” state duration T timer n is set by Tn: ⋅ TnPRE = T nhPWM f system PWMn Output T nhPWM Figure 12. PWM Timing illustration Divide by System Clk TnPRE + 1 Figure 13. ...

Power On Reset (Brown-Out Detection) The Power On Reset functionality detects power-on and brown-out situations, and includes glitch immunity and hysteresis for noise and transient stability. The power on reset functionality is disabled using the dedicated POR_E pin. Grounding ...

... Watchdog timer is cleared. Watchdog timer prescaler control. WDTPRE(1:0) controls the division of the main crystal oscillator clock to generate the watchdog timer clock 2048 WDT XOSC 4096 WDT XOSC 8192 WDT XOSC 16384 WDT XOSC SWRS047A CC1010 from Power- must periodically Page 63 of 146 ...

System clock WDTCLR Setting different prescaler combined with different Main Crystal Oscillator frequencies, generates reset at an interval of: WDTPRE.1 WDTPRE Table 21. Watchdog Timer timing 16.5.1 Disabling the Watchdog Timer The ...

WDT |= 0x10; // Set WDTSE WDT &= ~0x08; // Clear WDTEN } 16.6 Real-time Clock The real-time clock can interrupts with intervals ranging from 1 to 127 seconds connected to the 32.768 ...

Serial Port 0 and 1 Two serial ports, serial port 0 and 1, are implemented. They are controlled through the SCON0 and SCON1 control register. The data is buffered in SBUF0 and SBUF1. Serial port 0 may be used ...

SBUF0 (0x99) - Serial Port 0, data buffer Bit Name R/W Reset value 7:0 SBUF0(7:0) R/W 0x00 SBUF1 (0xC1) – Serial Port 1, data buffer Bit Name R/W Reset value 7:0 SBUF1(7:0) R/W 0x00 SCON0 (0x98) - Serial Port 0 ...

SCON1 (0xC0) - Serial Port 1 Control Register Bit Name R/W Reset value 7 SM0_1 R R/W 0 SM1_1 5 SM2_1 R REN_1 R TB8_1 R RB8_1 R TI_1 R/W ...

The clock output is high when the serial port is idle. In reception, data is shifted in on the rising edge of the clock. In Baudrate (kBaud xosc xosc 3.6864 7.3728 MHz MHz 57.6 1/255 1/254 19.2 ...

RB8_0 / RB8_1) and the receive interrupt flag is set. If not, the received data is lost and RB8_0 / RB8_1 and the receive interrupt flag remains unchanged. 16.7.3 MODE2 Mode 2 provides asynchronous ...

... SCK, the serial data output pin MO and the serial data input pin MI. The direction bits set in P0DIR(0) and P0DIR(2) are then ignored, setting SCK CC1010 as an output and input. The to direction bit P0DIR(1) still determines the direction of the master data output pin MO. ...

SPCR (0xA1) - SPI Control Register Bit Name R/W Reset value R SPE R DORD R R/W 0 CPOL 2 CPHA R/W 0 1:0 SPR(1:0) R/W 0 ...

... SPDR is ignored and the data must be written to SPDR again for sent SCK CC1010 Figure 17. Two-wire serial interface It is also possible to check the SPI status bit, SPSR.SPA, before writing to SPDR to avoid collisions. This bit is set only when data is being transmitted. ...

SPDR is written by 8051 here, while SPCR.SPE is active SCK (CPOL=0, CPHA=0) SCK (CPOL=0, CPHA=1) SCK (CPOL=1, CPHA=0) SCK (CPOL=1, CPHA= DORD DORD=1 SPSR.SPA SPDR read by 8051 Data ...

... DES O=E O=D The following is an example on how to use the single DES algorithm hardware in CC1010 . First the 56-bit encryption key must be stored in the external RAM. Then the CRPKEY register must be written to point to the start of the encryption key. Note that the encryption key must start on a RAM address location divisible by 8 ...

CRPCON.CRPEN goes low and the DES interrupt flag is set. The external RAM will now contain the encrypted data bit stream Key K 1 Table 24. DES key location in RAM Encryption / decryption is done in-place, ...

CRPCON (0xC3) - Encryption / Decryption Control Register Bit Name R/W Reset value CRPIE R CRPIF R LOADKEYS R CRPMD R ENCDEC R TRIDES R/W0 ...

... Reset value 7:0 CRPINIn R/W 0x00 (7:0) 16.10 Random Bit Generation CC1010 can generate real random bit sequences to be used as encryption keys, seed for a software pseudo random generator or other purposes. The data is generated from amplifying noise in the RF receiver path. To enable random bit generation, set and RANCON ...

ADC The on-chip 10-bit ADC is controlled by the registers ADCON and ADCON2. Three analog pins can be sampled, selected by ADCON.ADADR. This register is also used to select the AD1 pin as external reference (when using AD0). When ...

In single-conversion mode conversion is initiated by setting the ADCON.ADCRUN control bit. The ADC interrupt flags EXIF.ADIF ADCON2.ADCIF are set by hardware if the 8 MSB of the latest sampled ...

ADCON (0x93) - ADC Control Register Bit Name R/W Reset value 7 AD_PD R 5:4 ADCM(1:0) R ADCREF R R/W 0 ADCRUN 1:0 ADADR(1:0) R/W 00 ADDATL (0x94) - ADC Data ...

ADCON 2(0x96) - ADC Control Register 2 Bit Name R/W Reset value 7 ADCIE R ADCIF R/W 0 5:0 ADCDIV R/W 0x00 ADTRH (0x97) - ADC Threshold Register Bit Name R/W Reset value 7:0 ADTRH(7:0) R/W 0x00 Description ...

... Very few external passive components are required for Transceiver. transceiver The key parameters for the RF transceiver are listed in Table 6, Table 7, Table 8, Table 9, and Table 10, starting page 8. CC1010 CC1010 a AD2(RSSI/IF) DEMOD IF STAGE ENCODER /N ~ CHARGE PD LPF ...

... CC1010 In receive mode the is configured as a traditional super-heterodyne receiver. The RF input signal is amplified by the low-noise amplifier (LNA) and converted down to the intermediate frequency (IF) by the mixer (MIXER). In the intermediate frequency stage (IF STAGE) this down- converted signal is amplified and filtered before being fed to the demodulator (DEMOD) ...

... The placement and size of the decoupling capacitors and power supply filtering are very important sensitivity and lowest possible LO leakage matching and the reference layouts should be followed. ® Studio SWRS047A performance in specific circuit). These capacitors CC1010 . to achieve the best Page 85 of 146 ...

... C42 6 C41 L41 L32 7 8 AVDD 9 10 L101 R131 16 Figure 20. Typical Note: Decoupling capacitors not shown. Please see CC1010EM reference design. DVDD (Top view) AVDD AVDD AGND RF_IN RF_OUT AVDD AGND AGND AGND L1 L2 AVDD CHP_OUT R_BIAS AVDD AGND XTAL ...

Item 433 MHz C31 10 pF, 5%, C0G, 0603 C41 6.8 pF, 5%, C0G, 0603 C42 8.2 pF, 5%, C0G, 0603 C171 18 pF, 5%, C0G, 0603 C181 18 pF, 5%, C0G, 0603 L32 68 nH, 10%, 0805 (Coilcraft 0805CS-680XKBC) ...

... Chipcon Developer’s Newsletter to be notified of updates. Figure 21 shows the user interface of ® SmartRF Studio. with a ® Studio, ® Figure 21. SmartRF Studio SWRS047A CC1010 RF ® Studio will provide the ® Studio can guarantee across ® Studio software, Page 88 of 146 ...

... R0 0 the part, the TX synthesiser and the crystal oscillator. This individual control can be used to optimise CC1010 for lowest possible current consumption in a certain application. A typical power-on sequence for minimum battery- power consumption is shown in Figure 22. The figure assumes that frequency A is through used for RX and frequency B is used for TX ...

RF Power Down TX? Turn on RX: RFMAIN: RXTX = 0, F_REG = 0 RX_PD = 0, FS_PD = 0 CURRENT = ‘RX current’ Wait 250 µs RX mode Turn off RX: RFMAIN: RX_PD = 1, FS_PD ...

Data Modem and Data Modes Four different data modes are defined for transmission and reception, programmable through MODEM0.DATA_FORMAT. These modes differ in data encoding, how incoming and outgoing data is delivered and accepted, and resynchronisation of the bitstream is ...

TX data Figure 23. Manchester encoding Transparent mode Baudrate User defined configuration Data encoding User defined Data Input & RFBUF(0) Output Clock N/A Regeneration Bitmode/ N/A Bytemode Preamble N/A detection Table 29. Properties of different data modes (MODEM0.DATA_FORMAT ...

MODEM0 (0xDB) - Modem Control Register 0 Bit Name 7:5 BAUDRATE(2:0) 4:3 DATA_FORMAT (1:0) 2:0 XOSC_FREQ (2:0) R/W Reset value Description R/W 011 000 : 0.6 kBaud 001 : 1.2 kBaud 010 : 2.4 kBaud 011 : 4.8 kBaud 100 ...

Baud rates Baud rates from 0.6 kBaud to 76.8 kBaud are programmable control MODEM0.BAUDRATE MODEM0.XOSC_FREQ must also be set = RF _ BAUDRATE RF_BAUDRATE is the output baud rate in kBaud, BAUDRATE and XOSC_FREQ are control bits in MODEM0. ...

Transmitting and receiving data In the Transparent or UART modes outgoing and incoming data is routed directly to the modulator in transmit mode and directly from the demodulator in receive mode. In the NRZ and Manchester RF Transmitter Modulator ...

In order to start transmission of data as quickly as possible, the first bit/byte to be transmitted should be written to RFBUF before the modulator is (RFMAIN.TX_PD=0). It will immediately ...

Demodulation and data decision A block diagram of the digital demodulator is shown in Figure 25. The IF signal is sampled and its instantaneous frequency is detected. The result is decimated and filtered. In the data slicer the data ...

XOSC f s MODEM . 0 XOSC _ FREQ = − ⋅ ⋅ IF 150 kHz 2 f XTAL low RF and ∆f is the deviation. SmartRF may be used to configure this correctly. Frequency Sampler detector ...

Noise Noise Averaging filter always free-running Averaging filter always free-running Figure 28. Free-running averaging filter Settling Manual Lock NRZ mode MODEM1.LOCK_ MODEM1. SETTLING AVG_MODE ='1' MODEM1.LOCK_ (1:0) AVG_IN ='0'=→’1’** ...

MODEM1 (0xDA) - Modem Control Register 1 Bit Name R LOCK_AVG_IN R/W 5 LOCK_AVG_MODE R/W 4 LOCK_AVG_STAT R 3:2 SETTLING(1:0) R/W 1 R/W PEAKDETECT 0 MODEM_RESET_N R/W MODEM2 (0xD9) - Modem Control Register 2 Bit Name ...

RFCON (0xC2 Control Register Bit Name R/W Reset value 7 MVIOL R 0 3:1 R/W 011 MLIMIT(2:0) 0 R/W 0 BYTEMODE Description Reserved, read as 0 Manchester code violation status of current bit in ...

... Synchronization and preamble detection Most RF communication protocols will have a preamble designated to let the receiver synchronise reception on a bit CC1010 and byte level. contains hardware that will perform these tasks easily in synchronous NRZ and Manchester encoded modes. The byte synchronization ensures that the framing of bytes in the ...

... Furthermore, violations of the Manchester coding format is reported in the status bit RFCON.MVIOL. The SWRS047A to the start of the zero-one sequence. be DC-balanced once to facilitate reception and of such special cases, CC1010 of a reception or Page 103 of 146 ...

Manchester coding violation can be configured in RFCON.MLIMIT. RFCON.MVIOL is set when, in bitmode, the currently available bit in RFBUF.0 was determined to violate Manchester coding bytemode, when one or more of ...

Receiver sensitivity versus data rate and frequency separation The receiver sensitivity depends on the data rate, the data format, FSK frequency separation and the RF frequency. Typical figures for the receiver sensitivity (BER = - are shown ...

Figure 31. Sensitivity versus frequency offset, 868 MHz, 2.4 kBaud Manchester -98 -99 -100 -101 -102 -103 -104 -105 -106 -107 -108 -80 -60 -40 ...

Frequency programming RX mode: f (low-side mode (Lower FSK frequency) Figure 33, Relation between f The frequency synthesiser controlled by the frequency word in the configuration registers. There are two frequency words, A ...

... Chipcon recommends using the frequency settings described in the Recommended Settings for ISM Frequencies section on page 111. Chipcon recommends the use of the SmartRF calculate RF settings for the CC1010. Using the Print registers to file option in is set sep the File menu generates a text file with a C ...

FREQ_0B (0xCD) - Frequency B, Control Register 0 Bit Name R/W 7:0 FREQ_B(7:0) R/W FSEP1 (0xEB) - Frequency Separation Control Register 1 Bit Name R/W Reset value 7 2:0 FSEP(10:8) R/W 0x00 FSEP0 (0xEA) - Frequency Separation ...

Lock Indication The frequency synthesis PLL has a lock indicator, which can be read from the LOCK register. LOCK_INSTANT is a single sample of the phase difference between the reference frequency and the divided VCO frequency. This bit gives ...

Recommended Settings for ISM Frequencies The recommended frequency synthesiser settings for a few operating frequencies in the popular ISM bands are shown in Table 35. These settings ensure configuration of the synthesiser in receive mode for best sensitivity. For ...

ISM Actual Crystal Frequency frequency frequency [MHz] [MHz] [MHz] 869.525 869.506000 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 869.85 869.860400 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 915 915.018800 3.6864 7.3728 11.0592 14.7456 18.4320 22.1184 *Note: When using high-side LO injection the ...

VCO Only one external inductor (L101) is required for the VCO. The inductor will determine the operating frequency range of the circuit important to place the inductor as close to the pins as possible in order to ...

... Used in RX mode 1 : use CHP_CO[4:0] value. Used in TX mode 0x10 Charge pump current DAC override value, applied when CHP_OVERRIDE 0x1B in TX mode. SWRS047A and respectively. and CC1010 , but must manually be flag) . See the main text. REF is high. Use Page 114 of 146 ...

TEST5 (0xFE) – PLL Test Register 5 Bit Name R/W 7 CHP_DISABLE R/W 4 VCO_OVERRIDE R/W 3:0 VCO_AO(3:0) R/W TEST4 (0xFD) – PLL Test Register 4 Bit Name R/W 7:6 - R/W 5:0 L2KIO R/W TEST3 (0xFC) ...

Start single calibration Start single calibration Write FREQ_A, FREQ_B Write FREQ_A, FREQ_B Write CAL.CAL_DUAL = 0 Write CAL.CAL_DUAL = 0 Write RFMAIN: Write RFMAIN: RXTX = 0; F_REG = 0; RX_PD = 0; TX_PD = 1; RXTX = 0; F_REG ...

Start dual calibration Start dual calibration Write FREQ_A, FREQ_B Write FREQ_A, FREQ_B Write CAL.CAL_DUAL = 1 Write CAL.CAL_DUAL = 1 Write RFMAIN: Write RFMAIN: RXTX = 0; F_REG = 0; RX_PD = 0; TX_PD = 1; RXTX = 0; F_REG ...

VCO, LNA and buffer current control The VCO current is programmable and should be set according to operating frequency, RX/TX mode and output power. The receiver sensitivity will also be affected by the current Recommended settings CURRENT.VCO_CURRENT bits are ...

FREND (0xEE) - Front End Control Register Bit Name 7 BUF_CURRENT 4:3 LNA_CURRENT(1:0) 2 IF_EXTERNAL 1 RSSI 0 - R/W Reset value Description R/W 0 Reserved, should always be written 0 R/W 0 Control of current in the ...

... Description Selects matching capacitor array value for RX, step size is 0.4 pF 0000: Use for RF frequency > 500 MHz 1100: Use for RF frequency < 500 MHz Selects matching capacitor array value for TX, step size is 0.4 pF. Recommended setting is 0000 SWRS047A RF_IN RF_OUT CC1010 Page 120 of 146 ...

Figure 37. Typical LNA input impedance, 300 – 1000 MHz SWRS047A Page 121 of 146 ...

Figure 38. Typical inactive PA pin impedance, 300 – 1000 MHz SWRS047A Page 122 of 146 ...

... MCU and RF transceiver). If the crystal frequency is changed, the current consumption for the MCU will change, the relationship between crystal frequency and MCU current consumption is shown in Figure 1. Table 37. Output power settings and typical current consumption CC1010 the entire transceiver and MCU active. In power down mode the PA_POW should be set to 0x00 for minimum leakage current ...

Output power Figure 39. Typical output power and total current consumption, 433 MHz 40,0 30,0 20,0 10,0 0,0 -10,0 ...

PA_POW (0xE2 Output Power Control Register Bit Name R/W 7:4 PA_HIGHPOWER R/W (3:0) 3:0 R/W PA_LOWPOWER (3:0) Reset value Description 0x00 Control of output power in high power array. Should be 0000 in PD mode. See Table 37 ...

... This RSSI voltage can be measured by the on-chip A/D converter using the AD2 input. Note that a higher voltage means a lower input signal. CC1010 AD2 (RSSI/IF) C281 Figure 41. RSSI circuit The RSSI measures the power referred to the RF_IN pin. The input power can be ...

... CC1010 , a 10.7 MHz ceramic filter, SAW front-end filter and an external 10.7 MHz demodulator. The matching network for an CC1010 external IF filter is shown in Figure 43. R281 = 470 Ω , C281 = 3.3nF. This external network provides a 330 Ω source impedance for the 10.7 MHz ceramic filter. ...

Optional LC Filter An optional low-pass LC filter may be added between the antenna and the matching network in certain applications. The filter will reduce the emission of harmonics and increase the receiver selectivity. The filter topology is shown ...

... RTC_IRQ Table 39. TESTMUX modes Reset value Description 0x00 Reserved, read as 0 0xXX Reserved for future use. Reset value Description 0x2F Reserved for future use. SWRS047A CC1010 , but is included P0.0 Normal operation MODEM_TX_OUT ANALOG_WINDOW_SYNC TIMER3_IRQ DES_IRQ CAL_DIG_COMPLETE ANALOG_IF_OUT MODEM_TX_OUT ADC_SAR_EOC CLK_UC Page 129 of 146 ...

FSCTRL (0xEC) - Frequency Synthesiser Control Register Bit Name R/W Reset value 7 0x00 4 EXT_FILTER R DITHER1 R DITHER0 R SHAPE R FS_RESET_N R/W 1 PRESCALER (0xE6) - Prescaler ...

... Power down modes and clock modes of the MCU will also reduce the power consumption significantly. See page 33 for details. Also of interest is Application Note AN017 Low Power Systems Using the CC1010, available on Chipcon’s web site. 19.4 Narrow-band systems CC400 CC900 , recommended for best performance in ...

... Chipcon supplies development kit for the includes everything you need to start and the finish your design. The development kit is documented in the CC1010DK User and Manual. The development hopping evaluation version of the Keil C compiler; this is limited to a code size of 2 kBytes. If ...

... For 868 and 915 MHz operation, some of the AVDD supply pins should be fitted with ferrite beads in 19.11 Antenna Considerations CC1010 can be used together with various types of antennas. The most common antennas for short-range devices are monopole, helical and loop antennas. ...

... For a more thorough primer on antennas, please refer to Application Note AN003 20. Package Description (TQFP-64) CC1010 is packaged in a TQFP-64 package. The package is shown in Figure 45. Please note that the drawing in Figure 45 is not to scale. 21. Soldering Information The recommended soldering profiles for both leaded and Pb-free packages are according to IPC/JEDEC J-STD-020 ...

SWRS047A Page 135 of 146 ...

SWRS047A Page 136 of 146 ...

List of Abbreviations • ADC - Analog to Digital Converter • AMR – Automatic Meter Reading • CFB - Cipher Feedback Mode • CMOS – Complementary Metal Oxide Semiconductor • CPU – Central Processor Unit • DES - Data ...

... SM0_0 SM1_0 0x99 SBUF0 SBUF0.7 SBUF0.6 0x9A . - - 0x9B - - - 0x9C - - - 0x9D - - - 0x9E - - - 0x9F CHVER CHIP_TYPE5 CHIP_TYPE4 CC1010 Bit 5 Bit 4 Bit 3 P0.5 P0.4 P0.3 SP.5 SP.4 SP.3 DPL0.5 DPL0.4 DPL0.3 DPH0.5 DPH0.4 DPH0.3 DPL1.5 DPL1.4 DPL1.3 DPH1.5 DPH1.4 DPH1 GF1 TF0 TR0 IE1 ...

... CRPINI7 CRPINI7.7 CRPINI7.6 0xC0 SCON1 SM0_1 SM1_1 0xC1 SBUF1 SBUF1.7 SBUF1.6 0xC2 RFCON - - 0xC3 CRPCON - CRPIE 0xC4 CRPKEY CRPKEY7 CRPKEY6 CC1010 Bit 5 Bit 4 Bit 3 P2.5 P2.4 P2.3 SPE DORD CPOL SPDR5 SPDR4 SPDR3 - - - - - P0DIR3 P1DIR5 P1DIR4 P1DIR3 P2DIR5 P2DIR4 P2DIR3 ...

... ACC ACC7 ACC6 0xE1 CURRENT VCO_CURRENT3 VCO_CURRENT2 0xE2 PA_POW PA_HIGHPOWER PA_HIGHPOWER 0xE3 PLL REFDIV4 REFDIV3 0xE4 LOCK - - 0xE5 CAL CAL_START CAL_DUAL CC1010 Bit 5 Bit 4 Bit 3 CRPDAT5 CRPDAT4 CRPDAT3 CRPCNT5 CRPCNT4 CRPCNT3 - - - RX_PD TX_PD FS_PD RFBUF5 RFBUF4 RFBUF3 FREQ_A5 FREQ_A4 FREQ_A3 FREQ_A13 ...

... TEST1 - - 0xFB TEST2 - - 0xFC TEST3 - - 0xFD TEST4 - - 0xFE TEST5 - - 0xFF TEST6 LOOPFILTER_ LOOPFILTER_ TP1 TP2 CC1010 Bit 5 Bit 4 Bit 3 PRE_CURRENT1 PRE_CURRENT0 IF_INPUT RESERVED.5 RESERVED.4 RESERVED.3 - RTCIE ET3 FSDELAY5 FSDELAY4 FSDELAY3 FSEP5 FSEP4 FSEP3 - - - - EXT_FILTER DITHER1 RT5 RT4 RT3 LNA_BUF_CUR ...

Alphabetic Register Index ACC (0xE0) - Accumulator Register........................................................................................ 23 ADCON (0x93) - ADC Control Register................................................................................... 81 ADCON 2(0x96) - ADC Control Register 2 ............................................................................. 82 ADDATH (0x95) - ADC Data Register, High Bits .................................................................... 81 ADDATL (0x94) - ADC ...

FREQ_2A (0xCC) – Frequency A, Control Register 2 .......................................................... 108 FREQ_2B (0xCF) - Frequency B, Control Register 2 ........................................................... 108 FSCTRL (0xEC) - Frequency Synthesiser Control Register ................................................. 130 FSDELAY (0xE9) - Frequency Shaping Delay Control Register........................................... 129 FSEP0 (0xEA) ...

RFMAIN (0xC8 Main Control Register ........................................................................... 89 RTCON (0xED) - Realtime Clock Control Register ................................................................. 65 SBUF0 (0x99) - Serial Port 0, data buffer ............................................................................... 67 SBUF1 (0xC1) – Serial Port 1, data buffer .............................................................................. 67 SCON0 (0x98) ...

... Package Device (1) Type CC1010PAG Active TQFP CC1010PAGR Active TQFP Orderable Evaluation Module Description CC1010DK-433 CC1010 Development Kit, 433 MHz CC1010DK-868 CC1010 Development Kit, 868/915 MHz Package Pins Package Eco Plan (2) Drawing Qty PAG 64 160 Green (RoHS & no Sb/Br) PAG 64 1500 Green (RoHS & ...

General Information 27.1 Document History Revision Date Description/Changes SWRS047A 2009-09-18 Removed logo from header New package description New ordering information Removed chapter on Package Marking Changes to chapter on Tray Specification SWRS047 2004-12-17 Added history table. Various corrections and ...

... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing CC1010PAGR TQFP PAG PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 64 1500 330.0 24.4 12.35 12.35 Pack Materials-Page 1 18-Sep-2009 Pin1 (mm) (mm) (mm) (mm) Quadrant 1.85 16 ...

... Device Package Type CC1010PAGR TQFP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) PAG 64 1500 Pack Materials-Page 2 18-Sep-2009 Width (mm) Height (mm) 378.0 70.0 346.0 ...

... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...