CYWUSB6935-28SEI Cypress Semiconductor Corp, CYWUSB6935-28SEI Datasheet - Page 11

• Manufacturer Part Number: CYWUSB6935-28SEI
• Description: IC WIRELESS USB 2.4GHZ 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-28SEI

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Other names: 428-1576-5

Document 38-16008 Rev. **
Bit
7:5
4
3
2
1:0
Bit
7:4
3
2:0
Name
Reserved
Receive Invert
Transmit Invert The Transmit Invert bit is used to invert the data that is to be transmitted.
Reserved
IRQ Pin Select The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin.
Name
Reserved
SERDES Enable The SERDES Enable bit is used to switch between bit-serial mode and SERDES mode.
EOF Length
7
7
Addr: 0x05
Addr: 0x06
Reserved
Description
These bits are reserved and should be written with zeros.
The Receive Invert bit is used to invert the received data.
This bit is reserved and should be written with zero.
1 = Inverted over-the-air Receive data
0 = Non-inverted over-the-air Receive data
1 = Inverted Transmit Data.
0 = Non-inverted Transmit Data.
11 = Open Drain (asserted = 0, deasserted = Hi-Z)
10 = Open Source (asserted = 1, deasserted = Hi-Z)
01 = CMOS (asserted = 1, deasserted = 0)
00 = CMOS Inverted (asserted = 0, deasserted = 1)
Description
These bits are reserved and should be written with zeros.
When the SERDES is enabled data can be written to and read from the IC one byte at a time, through the use of
the SERDES Data registers. The bit-serial mode requires bits to be written one bit at a time through the use of
the DIO/DIOVAL pins, refer to section 3.2. It is recommended that SERDES mode be used to avoid the need to
manage the timing required by the bit-serial mode.
The End of Frame Length bits are used to set the number of sequential bit times for an inter-frame gap without
valid data before an EOF event will be generated. When in receive mode and a valid bit has been received the
EOF event can then be identified by the number of bit times that expire without correlating any new data. The
EOF event causes data to be moved to the proper SERDES Data Register and can also be used to generate
interrupts. If 0 is the EOF length, an EOF condition will occur at the first invalid bit after a valid reception.
6
6
1 = SERDES enabled.
0 = SERDES disabled, bit-serial mode enabled.
Reserved
5
5
Figure 7-7. SERDES Control
Receive Invert
Figure 7-6. Configuration
PRELIMINARY
REG_SERDES_CTL
4
4
REG_CONFIG
Transmit Invert
SERDES
Enable
3
3
Reserved
2
2
EOF Length
1
1
CYWUSB6935
Default: 0x01
Default: 0x03
IRQ Pin Select
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