CYWUSB6935-28SEI Cypress Semiconductor Corp, CYWUSB6935-28SEI Datasheet - Page 16

• Manufacturer Part Number: CYWUSB6935-28SEI
• Description: IC WIRELESS USB 2.4GHZ 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-28SEI

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Other names: 428-1576-5

Note:
Document 38-16008 Rev. **
Bit
7:0
Bit
7:0
Bit
63:0
5.
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Note: The Valid bit in the Transmit SERDES Valid register (Reg 0x10) is used to mark whether the radio will send data or preamble during that bit time of the
data byte. Data is sent LSB first. The SERDES will continue to send data until there are no more VALID bits in the shifter. For example, writing 0x0F to the
Transmit SERDES Valid register (Reg 0x10) will send half a byte.
Name Description
Data
Name
Valid
7
7
Name
PN Codes
Address 0x18
Address 0x14
Addr: 0x0F
Addr: 0x10
Addr: 0x11-18
[5]
Transmit Data. The over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit
4, followed by bit 5, followed by bit 6, followed by bit 7.
Description
The Valid bits are used to determine which of the bits in the Transmit SERDES Data register (reg 0x0F) are valid.
1 = Valid transmit bit.
0 = Invalid transmit bit.
Description
The value inside the 8 byte PN code register is used as the spreading code for DSSS communication. All 8 bytes can
be used together for 64 chips/bit PN code communication, or the registers can be split into two sets of 32 chips/bit
PN codes and these can be used alone or with each other to accomplish faster data rates. Not any 64 chips/bit value
can be used as a PN code as there are certain characteristics that are needed to minimize the possibility of multiple
PN codes interfering with each other or the possibility of invalid correlation. The over-the-air order is bit 0 followed by
bit 1... followed by bit 62, followed by bit 63.
6
6
5
5
Address 0x17
Address 0x13
Figure 7-17. Transmit SERDES Valid
Figure 7-16. Transmit SERDES Data
PRELIMINARY
Figure 7-18. PN Code
4
REG_TX_VALID
4
REG_TX_DATA
REG_PN_CODE
Data
Valid
3
3
Address 0x16
Address 0x12
2
2
9
8
7
0x1E8B6A3DE0E9B222
6
1
1
CYWUSB6935
Default: 0x00
Default: 0x00
5
Address 0x15
Address 0x11
Default:
4
3
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2
0
0
1
0