CYWUSB6935-48LFI Cypress Semiconductor Corp, CYWUSB6935-48LFI Datasheet - Page 12

• Manufacturer Part Number: CYWUSB6935-48LFI
• Description: IC USB WIRELESS 2.4GHZ 48VQFN
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-48LFI

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Other names: 428-1578

Document 38-16008 Rev. **
Bit
7
6
5
4
3
2
1
0
Underflow B
Name
Underflow B
Overflow B
EOF B
Full B
Underflow A
Overflow A
EOF A
Full A
7
Addr: 0x07
Overflow B
Description
The Underflow B bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES
Data B register (Reg 0x0B)
An underflow condition occurs when attempting to read the Receive SERDES Data B register (Reg 0x0B) when it is
empty.
The Overflow B bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES
Data B register (Reg 0x0B)
An overflow condition occurs when new received data is written into the Receive SERDES Data B register (Reg
0x0B) before the prior data is read out.
The End of Frame B bit is used to enable the interrupt associated with the Channel B Receiver EOF condition.
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has
been detected, and then the number of invalid bits in the frame exceeds the number in the EOF length field. If 0 is
the EOF length, and EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by
reading the receive status register
The Full B bit is used to enable the interrupt associated with the Receive SERDES Data B register (Reg 0x0B) having
data placed in it.
A Full B condition occurs when data is transferred from the Channel B Receiver into the Receive SERDES Data B
register (Reg 0x0B). This could occur when a complete byte is received or when an EOF event occurs whether or
not a complete byte has been received.
The Underflow A bit is used to enable the interrupt associated with an underflow condition with the Receive SERDES
Data A register (Reg 0x09)
An underflow condition occurs when attempting to read the Receive SERDES Data A register (Reg 0x09) when it is
empty.
The Overflow A bit is used to enable the interrupt associated with an overflow condition with the Receive SERDES
Data A register (0x09)
An overflow condition occurs when new receive data is written into the Receive SERDES Data A register (Reg 0x09)
before the prior data is read out.
The End of Frame A bit is used to enable the interrupt associated with an End of Frame condition with the Channel
A Receiver.
The EOF IRQ asserts during an End of Frame condition. End of Frame conditions occur after at least one bit has
been detected, and then the number of invalid bits in a frame exceeds the number in the EOF length field. If 0 is the
EOF length, an EOF condition will occur at the first invalid bit after a valid reception. This IRQ is cleared by reading
the receive status register.
The Full A bit is used to enable the interrupt associated with the Receive SERDES Data A register (0x09) having
data written into it.
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data A
register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs whether or
not a complete byte has been received.
1 = Underflow B interrupt enabled for Receive SERDES Data B
0 = Underflow B interrupt disabled for Receive SERDES Data B
1 = Overflow B interrupt enabled for Receive SERDES Data B
0 = Overflow B interrupt disabled for Receive SERDES Data B
1 = EOF B interrupt enabled for Channel B Receiver.
0 = EOF B interrupt disabled for Channel B Receiver.
1 = Full B interrupt enabled for Receive SERDES Data B
0 = Full B interrupt disabled for Receive SERDES Data B
1 = Underflow A interrupt enabled for Receive SERDES Data A
0 = Underflow A interrupt disabled for Receive SERDES Data A
1 = Overflow A interrupt enabled for Receive SERDES Data A
0 = Overflow A interrupt disabled for Receive SERDES Data A
1 = EOF A interrupt enabled for Channel A Receiver.
0 = EOF A interrupt disabled for Channel A Receiver.
1 = Full A interrupt enabled for Receive SERDES Data A
0 = Full A interrupt disabled for Receive SERDES Data A
6
EOF B
5
Figure 7-8. Receive Interrupt Enable
PRELIMINARY
Full B
REG_RX_INT_EN
4
Underflow A
3
Overflow A
2
EOF A
1
CYWUSB6935
Default: 0x00
Page 12 of 32
Full A
0