CYWUSB6935-48LFI Cypress Semiconductor Corp, CYWUSB6935-48LFI Datasheet - Page 3

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CYWUSB6935-48LFI

Manufacturer Part Number
CYWUSB6935-48LFI
Description
IC USB WIRELESS 2.4GHZ 48VQFN
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYWUSB6935-48LFI

Frequency
2.4GHz
Data Rate - Maximum
62.5kbps
Modulation Or Protocol
DSSS, GFSK
Applications
AMR, ISM, RKE
Power - Output
0dBm
Sensitivity
-95dBm
Voltage - Supply
2.7 V ~ 3.6 V
Current - Receiving
57.7mA
Current - Transmitting
69.1mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Memory Size
-
Other names
428-1578

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Below are the requirements for the crystal to be directly
connected to X13IN and X13:
4.7
The RSSI register (Reg 0x22) returns the relative signal
strength of the ON-channel signal power and can be used to:
1) determine the connection quality, 2) determine the value of
the noise floor, and 3) check for a quiet channel before trans-
mitting.
The internal RSSI voltage is sampled through a 5-bit analog-
to-digital converter (ADC). A state machine controls the
conversion process. Under normal conditions, the RSSI state
machine initiates a conversion when an ON-channel carrier is
detected and remains above the noise floor for over 50uS. The
conversion produces a 5-bit value in the RSSI register (Reg
0x22, bits 4:0) along with a valid bit, RSSI register (Reg 0x22,
bit 5). The state machine then remains in HALT mode and
does not reset for a new conversion until the receive mode is
toggled off and on. Once a connection has been established,
the RSSI register can be read to determine the relative
connection quality of the channel. A RSSI register value lower
than 10 indicates that the received signal strength is low, a
value greater than 28 indicates a strong signal level.
To check for a quiet channel before transmitting, first set up
receive mode properly and read the RSSI register (Reg 0x22).
If the valid bit is zero, then force the Carrier Detect register
(Reg 0x2F, bit 7=1) to initiate an ADC conversion. Then, wait
greater than 50uS and read the RSSI register again. Next,
clear the Carrier Detect Register (Reg 0x2F, bit 7=0) and turn
the receiver OFF. Measuring the noise floor of a quiet channel
is inherently a 'noisy' process so, for best results, this
procedure should be repeated several times (~20) to compute
an average noise floor level. A RSSI register value of 0-10
indicates a channel that is relatively quiet. A RSSI register
value greater than 10 indicates the channel is probably being
used. A RSSI register value greater than 28 indicates the
presence of a strong signal.
Document 38-16008 Rev. **
• Nominal Frequency: 13 MHz
• Operating Mode: Fundamental Mode
• Resonance Mode: Parallel Resonant
• Frequency Stability:
• Series Resistance:
• Load Capacitance: 10 pF
• Drive Level: 10uW–100 uW
Receive Signal Strength Indicator (RSSI)
±
100 ohms
30 ppm
PRELIMINARY
5.0
5.1
The CYWUSB6935 has a four-wire SPI communication
interface between an application MCU and one or more slave
devices. The SPI interface supports single-byte and multi-byte
serial transfers. The four-wire SPI communications interface
consists of Master Out-Slave In (MOSI), Master In-Slave Out
(MISO), Serial Clock (SCK), and Slave Select (SS).
The SPI receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI
pin. Data to the application MCU is shifted out on the MISO
pin. The active-low Slave Select (SS) pin must be asserted to
initiate a SPI transfer.
The application MCU can initiate a SPI data transfer via a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes as shown in
Figure 5-1 through Figure 5-4. The SS signal should not be
deasserted between bytes. The SPI communications is as
follows:
The SPI communications interface has a burst mechanism,
where the command byte can be followed by as many data
bytes as desired. A burst transaction is terminated by
deasserting the slave select (SS = 1).
The SPI communications interface single read and burst read
sequences are shown in Figure 5-2 and Figure 5-3, respec-
tively.
The SPI communications interface single write and burst write
sequences are shown in Figure 5-4 and Figure 5-5, respec-
tively.
• Command Direction (bit 7) = “0” Enables SPI read transac-
• Command Increment (bit 6) = “1” Enables SPI auto address
• Six bits of address.
• Eight bits of data.
tion. A “1” enables SPI write transactions.
increment. When set, the address field automatically incre-
ments at the end of each data byte in a burst access, oth-
erwise the same address is accessed.
SPI Interface
Application Interfaces
CYWUSB6935
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