CYWUSB6932-28SEC Cypress Semiconductor Corp, CYWUSB6932-28SEC Datasheet - Page 15

• Manufacturer Part Number: CYWUSB6932-28SEC
• Description: IC WIRELESS USB 2.4GHZ 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6932-28SEC

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: HID, PC, Peripheral Gaming Devices
• Power - Output: 0dBm
• Sensitivity: -90dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 428-1579-5

Note:
Document 38-16007 Rev. *G
5.
Bit
7:4 Reserved
3
2
1
0
All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The
status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These
registers are read-only.
Name
Underflow
Overflow
Done
Empty
7
Addr: 0x0E
Description
These bits are reserved. This register is read-only.
The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register (Reg
0x0F) has occurred.
This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow occurs
when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES Data register (Reg
0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared by reading the Transmit
Interrupt Status register (Reg 0x0E).
The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register (0x0F)
has occurred.
This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow occurs
when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data has been sent.
This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
The Done bit is used to signal the end of a data transmission.
This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will only assert
after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt Status register (Reg
0x0E)
The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied.
This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit SERDES
Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It will be set when the
data is loaded into the transmitter, and it is ok to write new data.
1 = Underflow Interrupt pending.
0 = No Underflow Interrupt pending.
1 = Overflow Interrupt pending.
0 = No Overflow Interrupt pending.
1 = Done Interrupt pending.
0 = No Done Interrupt pending.
1 = Empty Interrupt pending.
0 = No Empty Interrupt pending.
6
Reserved
Figure 7-13. Transmit SERDES Interrupt Status
5
REG_TX_INT_STAT
4
Underflow
3
Overflow
2
Done
1
CYWUSB6932
CYWUSB6934
Default: 0x00
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