CYWUSB6934-28SEC Cypress Semiconductor Corp, CYWUSB6934-28SEC Datasheet - Page 9

• Manufacturer Part Number: CYWUSB6934-28SEC
• Description: IC WIRELESS USB 2.4GHZ 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6934-28SEC

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: HID, PC, Peripheral Gaming Devices
• Power - Output: 0dBm
• Sensitivity: -90dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 428-1580-5

Table 6. Data Rate
Table 7. Configuration
Notes
■ 001 – Not Valid
■ 010 – Not Valid
Document 38-16007 Rev. *J
3. The following Reg 0x04, bits 2:0 values are not valid:
Bit
7:2 Reserved
1:0 IRQ Pin Select The Interrupt Request Pin Select bits are used to determine the drive method of the IRQ pin.
7:3 Reserved
2
1
0
Bit
[3]
[3]
[3]
Code Width The Code Width bit is used to select between 32 chips/bit and 64 chips/bit PN codes.
Data Rate
Sample Rate The Sample Rate bit allows the use of the 12x sampling when using 32 chips/bit PN codes and Normal Data Rate.
7
7
Name
Name
Addr: 0x04
Addr: 0x05
These bits are reserved and should be written with zeroes.
1 = 32 chips/bit PN codes
0 = 64 chips/bit PN codes
The number of chips/bit used impacts a number of factors such as data throughput, range and robustness to
interference. By choosing a 32 chips/bit PN-code, the data throughput can be doubled or even quadrupled (when
double data rate is set). A 64 chips/bit PN code offers improved range over its 32 chips/bit counterpart as well
as more robustness to interference. By selecting to use a 32 chips/bit PN code a number of other register bits
are impacted and need to be addressed. These are PN Code Select (Reg 0x03, bit 5), Data Rate (Reg 0x04, bit
1), and Sample Rate (Reg 0x04, bit 0).
The Data Rate bit allows the user to select Double Data Rate mode of operation which delivers a raw data rate
of 62.5 kbits/sec.
1 = Double Data Rate - 2 bits per PN code (No odd bit transmissions)
0 = Normal Data Rate - 1 bit per PN code
This bit is applicable only when using 32 chips/bit PN codes which can be selected by setting the Code Width
bit (Reg 0x04, bit 2=1). When using Double Data Rate, the raw data throughput is 62.5 kbits/sec because every
32 chips/bit PN code is interpreted as 2 bits of data. When using this mode a single 64 chips/bit PN code is
placed in the PN code register. This 64 chips/bit PN code is then split into two and used by the baseband to offer
the Double Data Rate capability. When using Normal Data Rate, the raw data throughput is 32kbits/sec.
Additionally, Normal Data Rate enables the user to potentially correlate data using two differing 32 chips/bit PN
codes.
1 = 12x Oversampling
0 = 6x Oversampling
Using 12x oversampling improves the correlators receive sensitivity. When using 64 chips/bit PN codes or Double
Data Rate this bit is don’t care. The only time when 12x oversampling can be selected is when a 32 chips/bit PN
code is being used with Normal Data Rate.
These bits are reserved and should be written with zeroes.
11 = Open Source (IRQ asserted = 1, IRQ deasserted = Hi-Z)
10 = Open Drain (IRQ asserted = 0, IRQ deasserted = Hi-Z)
01 = CMOS (IRQ asserted = 1, IRQ deasserted = 0)
00 = CMOS Inverted (IRQ asserted = 0, IRQ deasserted = 1)
6
6
Reserved
5
5
Reserved
REG_DATA_RATE
4
4
REG_CONFIG
■ 011 – Not Valid
■ 111 – Not Valid.
Description
Description
3
3
Code Width
2
2
Data Rate
1
1
IRQ Pin Select
CYWUSB6934
CYWUSB6932
Default: 0x01
Default: 0x00
Sample Rate
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