CYRF6936-40LFXC Cypress Semiconductor Corp, CYRF6936-40LFXC Datasheet - Page 5

IC WIRELESS USB LP 40VQFN

CYRF6936-40LFXC

Manufacturer Part Number
CYRF6936-40LFXC
Description
IC WIRELESS USB LP 40VQFN
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CYRF6936-40LFXC

Frequency
2.4GHz
Data Rate - Maximum
1Mbps
Modulation Or Protocol
DSSS, GFSK
Applications
Remote Control
Power - Output
4dBm
Sensitivity
-97dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
21.2mA
Current - Transmitting
34mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
Interface
SPI
Termination Type
SMD
Bandwidth
876kHz
Supply Voltage Max
3.6V
Data Rate Max
1000Kbps
Frequency Band Type
ISM
Features
10
Frequency Band Range
2.400 - 2.483 GHz
Supply Voltage Min
2.4V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2024
CYRF6936-40LFXC

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CYRF6936-40LFXC
Manufacturer:
CYPRESS
Quantity:
210
Part Number:
CYRF6936-40LFXC
Manufacturer:
CRIIUS
Quantity:
20 000
In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used). To transmit data, the MCU must load the
data packet to be transmitted, set the length, and set the TX GO
bit. Similarly, when receiving packets in transaction mode,
firmware must retrieve the fully received packet in response to
an interrupt request indicating reception of a packet.
Data Rates
The CYRF6936 IC supports the following data rates by
combining the PN code lengths and data transmission modes
described in the previous sections:
Functional Block Overview
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power, range, and robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in seven steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 2. Internal PA Output Power Step Table
Frequency Synthesizer
Before transmission or reception may begin, the frequency
synthesizer must settle. The settling time varies depending on
channel; 25 fast channels are provided with a maximum settling
time of 100 μs.
The ‘fast channels’ (less than 100 μs settling time) are every third
channel, starting at 0 up to and including 72 (for example, 0, 3,
6, 9 …. 69, 72).
Document #: 38-16015 Rev. *H
1000 kbps (GFSK)
250 kbps (32 chip 8DR)
125 kbps (64 chip 8DR)
62.5 kbps (32 chip DDR)
31.25 kbps (64 chip DDR)
15.625 kbps (64 chip SDR)
PA Setting
7
6
5
4
3
2
1
0
Typical Output Power (dBm)
–13
–18
–24
–30
–35
+4
–5
0
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception, CRC16
generation and checking, and EOP detection and length field.
Packet Buffers and Radio Configuration Registers
Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet (as in the
CYWUSB6934). Configuration registers allow configuration of
DSSS PN codes, data rate, operating mode, interrupt masks,
interrupt status, and so on.
SPI Interface
The
communication between an application MCU and one or more
slave devices (including the CYRF6936). The SPI interface
supports single-byte and multi-byte serial transfers using either
4-pin or 3-pin interfacing. The SPI communications interface
consists of Slave Select (SS), Serial Clock (SCK), Master
Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data
(SDAT).
SPI communication may be described as the following:
The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI pin.
Data to the application MCU is shifted out on the MISO pin. The
active LOW Slave Select (SS) pin must be asserted to initiate an
SPI transfer.
The application MCU can initiate SPI data transfers using a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes shown in
Figure 4
The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
required. A burst transaction is terminated by deasserting the
slave select (SS = 1).
The SPI communications interface single read and burst read
sequences are shown in
respectively.
The SPI communications interface single write and burst write
sequences are shown in
respectively.
This interface may be optionally operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirectional
data pin (SDAT). When using 3-pin mode, user firmware must
ensure that the MOSI pin on the MCU is in a high impedance
state except when MOSI is actively transmitting data.
Command Direction (bit 7) = ‘1’ enables SPI write transaction.
A ‘0’ enables SPI read transactions.
Command Increment (bit 6) = ‘1’ enables SPI auto address
increment. When set, the address field automatically
increments at the end of each data byte in a burst access.
Otherwise the same address is accessed.
Six bits of address
Eight bits of data
CYRF6936
through
Figure 7
IC
has
on page 6.
Figure 5
Figure 7
an
SPI
and
and
Figure 6
Figure 8
interface
CYRF6936
Page 5 of 23
on page 6,
on page 6,
supporting
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