TRC101

Manufacturer Part NumberTRC101
DescriptionRFIC TRANCEIVER MULTI-CHANNEL FS
ManufacturerRFM
SeriesTRC
TRC101 datasheet
 


Specifications of TRC101

Frequency300MHz ~ 1GHzData Rate - Maximum256kbps
Modulation Or ProtocolFSKApplicationsGeneral Purpose
Power - Output8dBmSensitivity-105dBm
Voltage - Supply2.2 V ~ 5.4 VCurrent - Receiving17mA
Current - Transmitting28mAData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountOperating Temperature-40°C ~ 85°C
Package / Case16-TSSOPLead Free Status / RoHS StatusLead free / RoHS Compliant
Memory Size-Other names583-1093-2
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Complies with Directive 2002/95/EC (RoHS)
Product Overview
TRC101 is a highly integrated single chip, zero-IF, multi-channel, low
power RF transceiver. It is an ideal fit for low cost, high volume, two way
short-range wireless applications for use in the unlicensed 300-1000 MHz
frequency bands. All critical RF and baseband functions are completely
integrated in the chip, thus minimizing external component count and
simplifying and speeding design-ins. Use of a low cost, generic 10MHz
crystal and a low-cost microcontroller is all that is needed to create a
complete link. The TRC101 also incorporates different sleep modes to
reduce overall current consumption and extend battery life. Its small size
with low power consumption makes it ideal for various short range radio
applications.
Key Features
Modulation: FSK (Frequency Hopping Spread Spectrum
capability)
Frequency range: 300-1000 MHz
High sensitivity: (-105 dBm)
High data rate: Up to 256 kbps
Low current consumption
(RX current ~8.5mA)
Wide operating supply voltage: 2.2 to 5.4V
Low standby current (0.2uA)
Integrated PLL, IF, Baseband Circuitry
Automatic Frequency Adjust(TX/RX frequency alignment)
Programmable Analog/Digital Baseband Filter
Programmable Output RF Power
Programmable Input LNA Gain
Internal Valid Data Recognition
Transmit/Receive FIFO
Standard SPI Interface
TTL/CMOS Compatible I/O pins
Programmable CLK Output Freq
Automatic Antenna tuning circuit
Low cost, generic 10MHz Xtal reference
Integrated, Programmable Low Battery Voltage Detector
Programmable Wake-up Timer with programmable Duty Cycle
Integrated Selectable Analog/Digital RSSI
Integrated Crystal Oscillator
External Processor Interrupt pin
Programmable Crystal Load Capacitance
Programmable Data Rate
Integrated Clock & Data Recovery
Programmable FSK Deviation Polarity
External Wake-up Events
www.RFM.com
Email: info@rfm.com
©by RF Monolithics, Inc.
DEVELOPMENT KIT
(Info
Click
TRC101
300-1000 MHz
Transceiver
16-TSSOP package
Support for Multiple Channels
[315/433 Bands] 95 Channels (100kHz)
[868 Band] 190 Channels (100kHz)
[915 Band] 285 Channels (100kHz)
Power-saving sleep mode
Very few external components requirement
Small size plastic package: 16-pin TSSOP
Standard 13 inch reel, 2000 pieces.
Popular applications
Active RFID tags
Automated Meter reading
Home & Industrial Automation
Security systems
Two way Remote keyless entry
Automobile Immobilizers
Sports & Performance monitoring
Wireless Toys
Medical equipment
Low power two way telemetry systems
Wireless mesh sensors
Wireless modules
TRC101 - 4/8/08
here)
Page 1 of 42

TRC101 Summary of contents

  • Page 1

    ... Complies with Directive 2002/95/EC (RoHS) Product Overview TRC101 is a highly integrated single chip, zero-IF, multi-channel, low power RF transceiver ideal fit for low cost, high volume, two way short-range wireless applications for use in the unlicensed 300-1000 MHz frequency bands. All critical RF and baseband functions are completely integrated in the chip, thus minimizing external component count and simplifying and speeding design-ins ...

  • Page 2

    ... TRC101 Pin Configuration...................................................................................... 2 1.1 Pin Description..................................................................................................... 3 2.0 Functional Description ........................................................................................... 4 2.1 TRC101 Applications ........................................................................................... 4 RF Transmitter Matching ..................................................................................... 4 Antenna Design Considerations........................................................................... 5 PCB Layout Considerations ................................................................................. 5 3.0 TRC101 Functional Characteristics ....................................................................... 7 Input/Output Amplifier ................................................................................................ 7 Baseband Data and Filtering ..................................................................................... 7 Transmit Register....................................................................................................... 8 Receive FIFO............................................................................................................. 8 Automatic Frequency Adjustment (AFA).................................................................... 9 Crystal Oscillator........................................................................................................ 9 Frequency Control (PLL) and Frequency Synthesizer ...

  • Page 3

    ... Valid Data Detector Output– This pin may be configured to indicate Valid Data when the synchronous www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. TOP VIEW SDI nINT/DDET 1 16 SCK RSSIA 2 15 nCS VDD 3 14 SDO RF_N 4 13 TRC101 IRQ RF_P 5 12 GND 6 11 RESET 7 10 Xtal/Ref 8 9 The circuit contains an Page TRC101 - 4/8/08 ...

  • Page 4

    ... Functional Description The TRC101 is a low power, frequency agile, zero-IF, multi-channel FSK transceiver for use in the 315, 433, 868, and 916 MHz bands. All RF and baseband functions are completely integrated requiring only a single 10MHz crystal as a reference source and an external low-cost processor. Functions include: PLL synthesizer • ...

  • Page 5

    ... L3 Antenna Design Considerations The TRC101 is designed to drive a differential output such as a Dipole antenna or a Loop. The loop antenna is ideally suited for applications where compact size is required. The dipole is typically not an attractive option for compact designs due to its inherent size at resonance and distance needed away from a ground plane efficient antenna ...

  • Page 6

    ... Assembly View Top Side Bottom Side www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC101 - 4/8/08 ...

  • Page 7

    ... TRC101 Functional Characteristics LNA 0/ / Input/Output Amplifier The output power amplifier is an open-collector, differential output with programmable output power which can directly drive a loop or dipole antenna, and with proper matching may also drive a monopole antenna. Incorporated in the power amplifier is an automatic antenna tuning circuit to avoid manual tuning during production and to offset “ ...

  • Page 8

    ... The preamble may be one byte (Fast CR lock) or two bytes (Slow CR lock). The next two bytes should be the synchronous pattern. In this case, data storage begins immediately following the 2 other following bytes are treated as data. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. SYNCH BYTE 0x2D SYNCH BYTE 0XD4 DATA [N] DATA [N+2 DATA [N+1] nd synch byte. All Page TRC101 - 4/8/08 ...

  • Page 9

    ... Achieving higher data rates • Crystal Oscillator The TRC101 incorporates an internal crystal oscillator circuit that provides a 10MHz reference, as well as internal load capacitors. This significantly reduces the component count required. The internal load capacitance is programmable from 8.5pF to 16pF in 0.5pF steps. This has the advantage of accepting a wide range of crystals from many different manufacturers having different load capacitance requirements ...

  • Page 10

    ... The DQD is a unique function of the TRC101. The DQD circuit looks at the prefiltered incoming data and counts the “spikes” of noise for a predetermined period of time to get an idea of the quality of the link. This parameter is programmable through the Data Filter Command Register. The DQD count threshold is programmable from counts ...

  • Page 11

    ... RSSI output. Typically, Automatic Gain Control (AGC) is used to reduce the input signal level upon saturation of the RSSI in the presence of strong or near-field ASK signals. The TRC101 does not have an AGC option, however, the input LNA gain is programmable. The output RSSI signal level may be sampled upon enabling of the receiver to test if the signal level is in saturation ...

  • Page 12

    ... The TRC101 is equipped with a standard SPI bus that is compatible to almost all SPI devices. All functions and status of the chip are accessible through the SPI bus. Typical SPI devices are configured for byte write operations. The TRC101 uses word writes so the nCS pin(3) should be pulled low for 16 bits. ...

  • Page 13

    ... BBEN TXEN SYNEN OSCEN LBDEN WKUPEN CLKEN MUL6 MUL5 MUL4 MUL3 MUL2 DC5 DC4 DC3 DC2 DC1 CLK1 CLK0 LBD4 LBD3 LBD2 Page TRC101 - 4/8/08 POR Bit Bit Value 1 0 OFF1 OFF0 - - CAP1 CAP0 8008h OFFEN AFEN C4F7h PWR1 PWR0 9800h ...

  • Page 14

    ... AFA has to be disabled during the read by clearing the "AFEN" bit in the AFA Register (bit 0). To read the status register, initiate a command beginning with a ‘0’ and read the remaining bits on the SDO line. All other commands begin with a ‘1’ so the TRC101 recognizes a command vs. status. See figure 4 for timing reference. www.RFM.com Email: info@rfm.com © ...

  • Page 15

    ... Email: info@rfm.com ©by RF Monolithics, Inc. Figure 4. Status Read Timing Page TRC101 - 4/8/08 ...

  • Page 16

    ... DATEN FIFEN BAND1 TABLE 3. Frequency Band BAND1 BAND0 315 0 0 433 0 1 868 1 0 916 1 1 TABLE 4. Crystal Load CAP2 CAP1 CAP0 Capacitance Bit Bit Bit Bit Bit BAND0 CAP3 CAP2 CAP1 CAP0 Page TRC101 - 4/8/08 ...

  • Page 17

    ... Automatic Frequency Adjust Register. Bit [7..6] – Mode Selection: These bits select Automatic or Manual operation. When set to Manual operation, the TRC101 will take a sample when a strobe signal (See Bit [3]) is written to the register. There are four modes of operation. See Table 5 below for configuration. ...

  • Page 18

    ... PLL that tunes the desired carrier frequency. Bit [0] – Offset Frequency Enable: This bit, when set, enables the TRC101 to calculate the offset frequency by the sample taken from the Automatic Frequency Adjustment circuit. ...

  • Page 19

    ... DEV3 DEV2 DEV1 TABLE 7. Hex DEV3 DEV2 TABLE 8. PWR2 PWR1 Max 0 0 -3dB 0 0 -6dB 0 1 -9dB 0 1 -12dB 1 0 -15dB 1 0 -18dB 1 1 -21dB 1 1 Bit Bit Bit Bit Bit DEV0 0 PWR2 PWR1 PWR0 DEV1 DEV0 PWR0 Page TRC101 - 4/8/08 ...

  • Page 20

    ... Figure 6. Sequential Byte Write Timing www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit TX7 TX6 TX5 FIGURE 5. Initial TX Register Setting DATA BYTE 1 DATA BYTE 2 Bit Bit Bit Bit Bit Bit TX4 TX3 TX2 TX1 TX0 DATA BYTE 3 Page TRC101 - 4/8/08 0 ...

  • Page 21

    ... MHz c VAL <3903. VAL TABLE 9. Range B1 B0 315 MHz 1 31 433 MHz 1 43 868 MHz 2 43 916 MHz 3 30 Bit Bit Bit Bit Bit Freq4 Freq3 Freq2 Freq1 2.5 kHz 2.5 kHz 5.0 kHz 7.5 kHz Page TRC101 - 4/8/08 Bit 0 Freq0 ...

  • Page 22

    ... Bit [9..8] – Valid Data Detector Response Time: When Pin 16 is selected as Valid Data Detector output these bits set the response time in which the TRC101 will detect the incoming synchronous bit pattern and issue an interrupt to the host processor. See Table 11 below for response settings. ...

  • Page 23

    ... RSSI = RSSIthres + |GainLNA| www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Table 12. BB2 BB1 BB0 Resvd 0 0 400 0 0 340 0 1 270 0 1 200 1 0 134 Reserved 1 1 Table 13. LNA GAIN (dB) GAIN1 GAIN0 - - Table 14. RSSI2 RSSI1 RSSI0 -103 - - - - - Resvd Resvd Page TRC101 - 4/8/08 ...

  • Page 24

    ... As the data rate << deviation, a higher threshold parameter is permitted and may report good signal quality. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit CRLK CRLC 1 FILT Filter Type FILT (Bit 4) Digital 0 Analog (30,000*Data Rate) FILT Bit Bit Bit Bit DQLVL2 DQLVL1 DQLVL0 Page TRC101 - 4/8/08 ...

  • Page 25

    ... FIFO or data errors will occur. For a 10MHz ref xtal the max SCK <2.5MHz. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit RX7 RX6 RX5 Bit Bit Bit Bit RX4 RX3 RX2 RX1 when reading the XTAL Page TRC101 - 4/8/08 Bit 0 RX0 ...

  • Page 26

    ... Note: Clearing this bit will issue a FIFO reset. See Figure 9 for FIFO write and reset configuration. Figure 9. FIFO Write and Reset Configuration Bit [0] – Disable RESET Mode: When cleared, if the TRC101 encounters a 0.2V spike in the power supply, the glitch could cause a system reset. When set, this mode is disabled. www.RFM.com Email: info@rfm.com © ...

  • Page 27

    ... BR is the expected data rate as set above using BITR[6..0]. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit PRE BITR6 BITR5 BITR4 Fast mode = ΔBR/BR < 3/( Bit Bit Bit Bit BITR3 BITR2 BITR1 BITR0 ] -1 exp Page TRC101 - 4/8/08 ...

  • Page 28

    ... NOTE: If this bit is cleared, the oscillator will continue to run even though the Crystal Oscillator Enable bit (3) is cleared and the device will not fully enter sleep mode. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=8208h] Bit Bit Bit Bit Bit RXEN BBEN TXEN SYNEN Bit Bit Bit OSCEN LBDEN WKUPEN CLKDIS Page TRC101 - 4/8/08 Bit 0 ...

  • Page 29

    ... R4 R3 The Wake-up Timer Period register sets the wake-up interval for the TRC101. After setting the wake-up interval, the WKUPEN (bit 1 of Power Management Register) should be cleared and set at the end of every wake-up cycle. To calculate the wake-up interval desired, use the following: T (ms) = M[7 ...

  • Page 30

    ... Bit [7..1] – Duty Cycle Multiplier: These bits are the decimal value used to calculate the Duty Cycle or “On time” of the Receiver after the wake-up timer has brought the TRC101 out of sleep mode. Bit [0] – Duty Cycle Mode Enable: This bit enables the duty cycle mode when set. ...

  • Page 31

    ... Email: info@rfm.com ©by RF Monolithics, Inc. [POR=C000h] Bit Bit Bit Bit CLK2 CLK1 CLK0 LBD4 TABLE 15. Output Clock Frequency CLK2 CLK1 CLK0 (MHz Bit Bit Bit Bit Bit LBD3 LBD2 LBD1 LBD0 Page TRC101 - 4/8/08 ...

  • Page 32

    ... Band 14 433MHz Band mA 15 868MHz Band 17 916MHz Band 0.25 µA All blocks disabled Oscillator and baseband 3.5 mA enabled µA µA Programmable in 0.1 V 5.3 V steps mV 1000 mV -50dBm>RFin>-115dBm 0.3*Vdd µA Vil = µA Vih = Vdd, Vdd = 5.4 V 0.4 V Iol = Ioh = - Page TRC101 - 4/8/08 ...

  • Page 33

    ... Digital output rise/fall time www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc Load = 15 pF Page TRC101 - 4/8/08 ...

  • Page 34

    ... Band 916MHz Band Digital filters kbps Analog filter kHz Δdev = FSK deviation dBm RSSI signal goes high after input signal exceeds us programmed limit. CAPARRSI = 5 nF 315 MHz Band 433 MHz Band dBc 868 MHz Band 916 MHz Band Page TRC101 - 4/8/08 ...

  • Page 35

    ... Band 916MHz Band 315MHz Band 433MHz Band dBc 868MHz Band 916MHz Band 315MHz Band 433MHz Band pF 868MHz Band 916MHz Band 315MHz Band 433MHz Band 868MHz Band 916MHz Band 100 kHz from carrier dBc/Hz 1 MHz from carrier Page TRC101 - 4/8/08 ...

  • Page 36

    ... Calibrated every 30 seconds Unit Test Conditions MHz us within 1kHz settle, 10MHz step us Crystal running Programmable in 0.5 pF steps, pF tolerance +/- 10% ms Crystal ESR < 100 Ohms 315MHz Band (2.5kHz steps) 433MHz Band (2.5kHz steps) MHz 868MHz Band (5.0kHz steps) 916MHz Band (7.5kHz steps) Page TRC101 - 4/8/08 ...

  • Page 37

    ... All data rates are based -111 -109 -107 -105 -103 -101 -99 -97 -95 -93 -91 -89 -87 -85 1200 2400 www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. -3 BER. Sensitivity vs Data Rate 315MHz 433MHz 915MHz 868MHz 4800 9600 19200 38400 Data Rate (bps) 57600 115200 Page TRC101 - 4/8/08 ...

  • Page 38

    ... Current Consumption vs Voltage at Min/Max Data Rate 14.0 115Kbps 2.4Kbps 13.0 12.0 11.0 10.0 9.0 8.0 7.0 2.2 V www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. 915MHz 868MHz 433MHz 315MHz 3.0 V 5.4 V Voltage (V) Page TRC101 - 4/8/08 ...

  • Page 39

    ... Transmitter Measurement Results The transmitter measurements were derived from the Typical Application Circuit of Figure and the layout as suggested on pgs 5- 2.2V www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Output Power vs Voltage 3.0V Voltage (V) 315MHz 433MHz 868MHz 915MHz 5.4V Page TRC101 - 4/8/08 ...

  • Page 40

    ... Current Consumption vs Voltage (Max Output Power) 27.0 25.0 23.0 21.0 19.0 17.0 15.0 2.2V www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. 915MHz 433MHz 315MHz 3.0V Voltage (V) 868MHz 5.4V Page TRC101 - 4/8/08 ...

  • Page 41

    ... IPC/JEDEC J-STD-020C REFLOW PROFILE www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC101 - 4/8/08 ...

  • Page 42

    ... BSC. 0.19 0.30 0.007 0.65 BSC. 0.026 BSC. 0.80 0.90 1.05 0.031 0.035 1.20 0.50 0.60 0.75 0.020 0.024 1.00 REF. 0.39 REF 0.09 0.004 0.09 0.004 REF. 12 REF. 12 REF. 12 REF. Page TRC101 - 4/8/08 Max 0.177 0.201 0.012 0.041 0.47 0.030 8 ...