TRC101 RFM, TRC101 Datasheet - Page 10

• Manufacturer Part Number: TRC101
• Description: RFIC TRANCEIVER MULTI-CHANNEL FS
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC101

• Frequency: 300MHz ~ 1GHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: General Purpose
• Power - Output: 8dBm
• Sensitivity: -105dBm
• Voltage - Supply: 2.2 V ~ 5.4 V
• Current - Receiving: 17mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1093-2

The DQD is a unique function of the TRC101. The DQD circuit looks at the prefiltered incoming data and
counts the “spikes” of noise for a predetermined period of time to get an idea of the quality of the link.
This parameter is programmable through the Data Filter Command Register. The DQD count threshold is
programmable from 0 to 7 counts. The higher the count the lower the quality of the data link. This means
the higher the content of noise spikes in the data stream the more difficult it will be to recover clock
information as well as data.
Valid Data Detector
The DDET is an extension of the DQD. When incoming data is detected, it uses the DQD signal, the
Clock Recovery Lock signal, and the Digital RSSI signal to determine if the incoming data is valid. The
DDET looks for valid data transitions at an expected data rate. The desired data rate and the acceptance
criteria for valid data are user programmable through the SPI port. The DDET signal is valid when using
either the internal receive FIFO or an external pin to capture baseband data. The DDET has three modes
of operation: slow, medium, fast. Each mode is dependent on what signals it uses to determine valid data
as well as the number of incoming preamble bits present at the beginning of the packet. The DDET can
be disabled by the user so that only raw data from the comparator comes out, or it can be set to accept
only a preset range of data rates and data quality. The DDET saves battery power and time for a host
microprocessor because it will not wake up the microprocessor unless there is valid data present. See
the Receiver Control Register for a detailed description of the setup for valid data.
Receive Signal Strength Indicator (RSSI)
The TRC101 provides an analog RSSI and a digital RSSI. The digital RSSI threshold is programmable
through the Receiver Control Register and is readable through the Status Register only. When an
incoming signal is stronger than the preprogrammed threshold, the digital RSSI bit in the Status Register
is set.
The analog RSSI is available through the RSSIA external pin (15). This pin requires an external capacitor
which sets the settling time. The analog RSSI may be used to recover OOK/ASK modulated data. The
RSSI level is linear with input signal levels between -100 dBm and -55 dBm. The external capacitor value
will control the received ASK data rate allowed so choosing a lower value capacitor enables recovery of
faster data at the expense of amplitude. Using pin (15) with a sensitive comparator will yield good results.
The analog RSSI is available through and external pin (15). This pin requires an external capacitor which
sets the settling time. The analog RSSI may be used to recover ASK modulated data at a low rate on the
order of a few thousand bits per sec. The external capacitor value will control the received ASK data rate
allowed so choosing a lower value capacitor enables recovery of faster data at the expense of amplitude.
Using pin (15) with a sensitive comparator will yield good results.
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©by RF Monolithics, Inc.
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1.2
0.8
0.6
0.4
0.2
1
0
-112
-102
Input Power vs RSSI Voltage
-92
Input Power (dBm)
-82
-72
-62
-52
-42
TRC101 - 4/8/08
Page 10 of 42