TRC101 RFM, TRC101 Datasheet - Page 7

• Manufacturer Part Number: TRC101
• Description: RFIC TRANCEIVER MULTI-CHANNEL FS
• Manufacturer: RFM
• Series: TRCr

Specifications of TRC101

• Frequency: 300MHz ~ 1GHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK
• Applications: General Purpose
• Power - Output: 8dBm
• Sensitivity: -105dBm
• Voltage - Supply: 2.2 V ~ 5.4 V
• Current - Receiving: 17mA
• Current - Transmitting: 28mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 583-1093-2

RF _P
RF _N
T X /RX
3. TRC101 Functional Characteristics
Input/Output Amplifier
The output power amplifier is an open-collector, differential output with programmable output power which
can directly drive a loop or dipole antenna, and with proper matching may also drive a monopole antenna.
Incorporated in the power amplifier is an automatic antenna tuning circuit to avoid manual tuning during
production and to offset “hand effects”. Registers common to the Power Amplifier are:
The input LNA has selectable gain (0dB, -6dB, -14dB, -20dB) which may be useful in an environment with
strong interferers. The LNA has a 250ΩOhm differential input impedance which requires a matching
circuit when connected to 50 Ohm devices. Registers common to the LNA are:
Baseband Data and Filtering
The baseband receiver has several programmable options that optimize the data link for a wide range of
applications. The programmable functions include:
The receive bandwidth is programmable from 67kHz to 400kHz to accommodate various FSK modulation
deviations. If the deviation is known for a given transmitter, the best results are obtained with a
bandwidth at least twice the transmitter FSK deviation.
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©by RF Monolithics, Inc.
LNA
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P A
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Power Management Register
Receiver Control Register
Receive bandwidth
Receive data rate
Baseband Analog Filter
Baseband Digital Filter
Clock Recovery (CR)
Receive FIFO
Data Quality Detector
Valid Data Detector
Power Management Register
Transmit Configuration Register
0/90
V CO
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P LL
/N
Figure 2. Functional Block Diagram
X T A L/RE F
DE MOD
I/Q
OS C
F S K
A S K
RS S IA
RS S I
B A T T DE T
+
V DD
-
GND
CONT ROL
LOGIC
nRE S E T
TRC101 - 4/8/08
Page 7 of 42
R
S DI
S DO
S CK
nCS
nIRQ
DA T A / nF S E L
CR/F INT /F CA P
CLK OUT
nINT /DDE T