TRC102 RFM, TRC102 Datasheet

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TRC102

Manufacturer Part Number
TRC102
Description
RFIC TRANCEIVER MULTI-CHANNEL FS
Manufacturer
RFM
Series
TRCr
Datasheet

Specifications of TRC102

Frequency
400MHz ~ 1GHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK
Applications
General Purpose
Power - Output
5dBm
Sensitivity
-112dBm
Voltage - Supply
2.2 V ~ 3.8 V
Current - Receiving
12mA
Current - Transmitting
23mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Other names
583-1094-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TRC102
Manufacturer:
RFM
Quantity:
20 000
Complies with Directive 2002/95/EC (RoHS)
Product Overview
TRC102 is a highly integrated single chip, zero-IF, multi-channel, low
power RF transceiver. It is an ideal fit for low cost, high volume, two way
short-range wireless applications for use in the unlicensed 400-1000 MHz
frequency bands. The TRC102 is FCC & ETSI certifiable and improves
upon the TRC101 with improved phase noise and is capable of higher
output power. All critical RF and baseband functions are completely
integrated in the chip, thus minimizing external component count and
simplifying and speeding design-ins. Use of a low cost, generic 10MHz
crystal and a low-cost microcontroller is all that is needed to create a
complete link. The TRC102 also incorporates different sleep modes to
reduce overall current consumption and extend battery life. Its small size
with low power consumption makes it ideal for various short range radio
applications.
Key Features
www.RFM.com
©by RF Monolithics, Inc.
Modulation: FSK (Frequency Hopping Spread Spectrum
capability)
Frequency range: 400-1000 MHz
High sensitivity: (-112 dBm)
High data rate: Up to 256 kbps
Low current consumption (RX current ~11mA)
Operating supply voltage: 2.2 to 3.8V
Low standby current (0.3uA)
Programmable Synch Byte
Integrated PLL, IF, Baseband Circuitry
Automatic Frequency Adjust(TX/RX frequency alignment)
Programmable Analog/Digital Baseband Filter
Programmable Output RF Power
Programmable Input LNA Gain
Internal Valid Data Recognition
Transmit/Receive FIFO
Standard SPI Interface
TTL/CMOS Compatible I/O pins
Programmable CLK Output Freq
Automatic Antenna tuning circuit
Low cost, generic 10MHz Xtal reference
Integrated, Programmable Low Battery Voltage Detector
Programmable Wake-up Timer with programmable Duty Cycle
Integrated Selectable Analog/Digital RSSI
Integrated Crystal Oscillator
External Processor Interrupt pin
Programmable Crystal Load Capacitance
Programmable Data Rate
Integrated Clock & Data Recovery
Programmable FSK Deviation Polarity
External Wake-up Events
Email: info@rfm.com
Popular applications
Support for Multiple Channels
Power-saving sleep mode
Very few external components requirement
Small size plastic package: 16-pin TSSOP
Standard 13 inch reel, 2000 pieces.
Automated Meter reading
Active RFID tags
Home & Industrial Automation
Security systems
Two way Remote keyless entry
Automobile Immobilizers
Sports & Performance monitoring
Wireless Toys
Medical equipment
Low power two way telemetry systems
Wireless mesh sensors
Wireless modules
[433 Bands] 95 Channels (100kHz)
[868 Band] 190 Channels (100kHz)
[915 Band] 285 Channels (100kHz)
400-1000 MHz
Transceiver
16-TSSOP package
DEVELOPMENT KIT
TRC102
(Info
Click
TRC102 - 4/8/08
Page 1 of 51
here)

Related parts for TRC102

TRC102 Summary of contents

Page 1

... RF transceiver ideal fit for low cost, high volume, two way short-range wireless applications for use in the unlicensed 400-1000 MHz frequency bands. The TRC102 is FCC & ETSI certifiable and improves upon the TRC101 with improved phase noise and is capable of higher output power. All critical RF and baseband functions are completely integrated in the chip, thus minimizing external component count and simplifying and speeding design-ins ...

Page 2

... Table of Contents Table of Contents........................................................................................................................1 1.0 TRC102 Pin Configuration ...................................................................................................2 1.1 Pin Description ..................................................................................................................3 2.0 Functional Description .........................................................................................................4 2.1 TRC102 Applications ........................................................................................................4 RF Transmitter Matching...................................................................................................4 Antenna Design Considerations........................................................................................5 PCB Layout Considerations ..............................................................................................5 3.0 TRC102 Functional Characteristics ....................................................................................7 Input/Output Amplifier .............................................................................................................7 Baseband Data and Filtering...................................................................................................7 Transmit Register....................................................................................................................8 Receive FIFO ..........................................................................................................................8 Programmable Synch Byte .....................................................................................................8 Automatic Frequency Adjustment (AFA) ...

Page 3

... Package Information.........................................................................................................41 www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC102 - 4/8/08 ...

Page 4

... Reading the first four (4) bits of the status register tells the source of the interrupt. This pin may be used www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. TOP VIEW SDI 1 16 SCK 2 15 nCS 3 14 SDO 4 13 TRC102 IRQ 5 12 DATA/nFSEL CLKOUT 8 9 nINT/DDET RSSIA VDD RF_N RF_P GND RESET Xtal/Ref The circuit contains an Page TRC102 - 4/8/08 ...

Page 5

... Valid Data Detector Output– This pin may be configured to indicate Valid Data when the synchronous pattern recognition circuit indicates potentially real incoming data. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC102 - 4/8/08 ...

Page 6

... Functional Description The TRC102 is a low power, frequency agile, zero-IF, multi-channel FSK transceiver for use in the 433, 868, and 916 MHz bands. All RF and baseband functions are completely integrated requiring only a single 10MHz crystal as a reference source and an external low-cost processor. Functions include: PLL synthesizer • ...

Page 7

... Table 2. Antenna Design Considerations The TRC102 is designed to drive a differential output such as a Dipole antenna or a Loop. The loop antenna is ideally suited for applications where compact size is required. The dipole is typically not an attractive option for compact designs due to its inherent size at resonance and distance needed away from a ground plane efficient antenna ...

Page 8

... Assembly View Top Side Bottom Side www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC102 - 4/8/08 ...

Page 9

... TRC102 Functional Characteristics LNA 0/ / Input/Output Amplifier The output power amplifier is an open-collector, differential output with programmable output power which can directly drive a loop or dipole antenna, and with proper matching may also drive a monopole antenna. Incorporated in the power amplifier is an automatic antenna tuning circuit to avoid manual tuning during production and to offset “ ...

Page 10

... The FIFO read clock (SCK) must be < f for a 10 MHz reference xtal. The receive FIFO may also be configured to fill only when valid data has been identified. The TRC102 has a synchronous pattern detector that watches incoming data for a particular pattern. When it sees this pattern it begins to store any data that follows. At the same time, if pin 16 is configured for Valid Data Detector output (See Receiver Control Register), this pin will go ‘ ...

Page 11

... The best method is using the SDO pin and the associated FIFO function pins. Programmable Synch Byte The TRC102 may be configured to use a synch character to signal valid incoming data. This character is divided into two bytes, SB1 and SB0. SB1 is fixed to 2Dh and is not programmable. SB0 is user configurable ...

Page 12

... Data Quality Detector (DQD) The DQD is a unique function of the TRC102. The DQD circuit looks at the prefiltered incoming data and counts the “spikes” of noise for a predetermined period of time to get an idea of the quality of the link. This parameter is programmable through the Data Filter Command Register. The DQD count threshold is programmable from counts ...

Page 13

... RSSI output. Typically, Automatic Gain Control (AGC) is used to reduce the input signal level upon saturation of the RSSI in the presence of strong or near-field ASK signals. The TRC102 does not have an AGC option, however, the input LNA gain is programmable. The output RSSI signal level may be sampled upon enabling of the receiver to test if the signal level is in saturation ...

Page 14

... SPI bus. Typical SPI devices are configured for byte write operations. The TRC102 uses word writes so the nCS pin(3) should be pulled low for 16 bits. The maximum clock for the SPI bus is 20 MHz. ...

Page 15

... Email: info@rfm.com ©by RF Monolithics, Inc. Figure 3. SPI Interface Timing Page TRC102 - 4/8/08 ...

Page 16

... MUL6 MUL5 MUL4 MUL3 MUL2 DC5 DC4 DC3 DC2 DC1 CLK1 CLK0 LBD4 LBD3 LBD2 BUF1 BUF0 XSU PDD DITH Page TRC102 - 4/8/08 POR Bit Bit Value 1 0 OFF1 OFF0 - - CAP1 CAP0 8008h OFFEN AFEN C4F7h PWR1 PWR0 9800h TX1 TX0 ...

Page 17

... AFA has to be disabled during the read by clearing the "AFEN" bit in the AFA Register (bit 0). To read the status register, initiate a command beginning with a ‘0’ and read the remaining bits on the SDO line. All other commands begin with a ‘1’ so the TRC102 recognizes a command vs. status. See figure 4 for timing reference. www.RFM.com Email: info@rfm.com © ...

Page 18

... Email: info@rfm.com ©by RF Monolithics, Inc. Figure 4. Status Read Timing Page TRC102 - 4/8/08 ...

Page 19

... Bit Bit Bit Bit Bit DATEN FIFEN BAND1 TABLE 3. Frequency Band BAND1 BAND0 433 0 868 1 916 1 TABLE 4. Crystal Load CAP2 CAP1 CAP0 Capacitance Bit Bit Bit Bit BAND0 CAP3 CAP2 CAP1 8 Page TRC102 - 4/8/08 Bit 0 CAP0 ...

Page 20

... Automatic Frequency Adjust Register. Bit [7..6] – Mode Selection: These bits select Automatic or Manual operation. When set to Manual operation, the TRC102 will take a sample when a strobe signal (See Bit [3]) is written to the register. There are four modes of operation. See Table 5 below for configuration. ...

Page 21

... PLL that tunes the desired carrier frequency. Bit [0] – Offset Frequency Enable: This bit, when set, enables the TRC102 to calculate the offset frequency by the sample taken from the Automatic Frequency Adjustment circuit. ...

Page 22

... DEV3 DEV2 DEV1 TABLE 7. Hex DEV3 DEV2 TABLE 8. PWR2 PWR1 Max 0 0 -3dB 0 0 -6dB 0 1 -9dB 0 1 -12dB 1 0 -15dB 1 0 -18dB 1 1 -21dB 1 1 Bit Bit Bit Bit DEV0 0 PWR2 PWR1 PWR0 DEV1 DEV0 PWR0 Page TRC102 - 4/8/08 Bit 0 ...

Page 23

... Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC102 - 4/8/08 ...

Page 24

... COMMAND SDO Figure 6. Sequential Byte Write Timing www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit TX7 TX6 DATA BYTE 1 DATA BYTE 2 Bit Bit Bit Bit Bit TX5 TX4 TX3 TX2 TX1 DATA BYTE 3 Page TRC102 - 4/8/08 Bit 0 TX0 ...

Page 25

... MHz c VAL <3903. VAL TABLE 9. Range B1 B0 433 MHz 1 43 868 MHz 2 43 916 MHz 3 30 Bit Bit Bit Bit Freq5 Freq4 Freq3 Freq2 Tuning Resolution 2.5 kHz 5.0 kHz 7.5 kHz Page TRC102 - 4/8/08 Bit Bit 1 0 Freq1 Freq0 ...

Page 26

... Bit [9..8] – Valid Data Detector Response Time: When Pin 16 is selected as Valid Data Detector output these bits set the response time in which the TRC102 will detect the incoming synchronous bit pattern and issue an interrupt to the host processor. See Table 11 below for response settings. ...

Page 27

... RF Monolithics, Inc. (continued) Table 12. BB2 BB1 Reserved 0 0 400 0 0 340 0 1 270 0 1 200 1 0 134 Reserved 1 1 Table 13. LNA GAIN (dB) GAIN1 GAIN0 -14 1 -20 1 Table 14. RSSI Thresh RSSI2 RSSI1 -103 Reserved 1 1 Reserved 1 1 BB0 RSSI0 Page TRC102 - 4/8/08 ...

Page 28

... Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC102 - 4/8/08 ...

Page 29

... As the data rate << deviation, a higher threshold parameter is permitted and may report good signal quality. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit CRLK CRLC 1 FILT Filter Type FILT (Bit 4) Digital 0 Analog (30,000*Data Rate) FILT Bit Bit Bit Bit DQLVL2 DQLVL1 DQLVL0 Page TRC102 - 4/8/08 ...

Page 30

... SCK. nCS SCK SDO D 7 nFSEL nFINT Figure. 8 Recommended FIFO Read Method Timing www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit RX7 RX6 RX5 Bit Bit Bit Bit RX4 RX3 RX2 RX1 Page TRC102 - 4/8/08 Bit 0 RX0 ...

Page 31

... The internal FIFO cannot be accessed faster than f FIFO or data errors will occur. For a 10MHz ref xtal the max SCK <2.5MHz. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. /4 when reading the XTAL Page TRC102 - 4/8/08 ...

Page 32

... Figure 9. FIFO Write and Reset Configuration www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=CA80h] Bit Bit Bit Bit Bit FINT3 FINT2 FINT1 FINT0 Table 15. SBL SB1 N/A Bit Bit Bit Bit Bit SBL FIFST FILLEN RSTEN SB0 D4 (programmable) D4 (programmable) Page TRC102 - 4/8/08 ...

Page 33

... Bit [0] – Disable RESET Mode: When cleared, if the TRC102 encounters a 0.2V spike in the power supply, the glitch could cause a system reset. When set, this mode is disabled. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC102 - 4/8/08 ...

Page 34

... FIFO and RESET Mode Configuration Register. This value is valid for a byte or word long synch character. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=CED4h] Bit Bit Bit Bit Bit SYNC7 SYNC6 SYNC5 SYNC4 Bit Bit Bit SYNC3 SYNC2 SYNC1 SYNC0 Page TRC102 - 4/8/08 Bit 0 ...

Page 35

... BR is the expected data rate as set above using BITR[6..0]. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Bit Bit Bit Bit Bit PRE BITR6 BITR5 BITR4 Fast mode = ΔBR/BR < 3/( Bit Bit Bit Bit BITR3 BITR2 BITR1 BITR0 Page TRC102 - 4/8/08 ...

Page 36

... See Battery Detect Threshold and Clock Output Register section for programming details. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. [POR=8208h] Bit Bit Bit Bit RXEN BBEN TXEN SYNEN Bit Bit Bit Bit OSCEN LBDEN WKUPEN TRC102 - 4/8/08 Bit 0 CLKDIS Page ...

Page 37

... NOTE: If bit (0) is cleared, enabling the clock output, the oscillator will continue to run even though the Crystal Oscillator Enable bit (3) is cleared and the device will not fully enter sleep mode. www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC102 - 4/8/08 ...

Page 38

... R4 R3 The Wake-up Timer Period register sets the wake-up interval for the TRC102. After setting the wake-up interval, the WKUPEN (bit 1 of Power Management Register) should be cleared and set at the end of every wake-up cycle. To calculate the wake-up interval desired, use the following: T (ms) = M[7 ...

Page 39

... Bit [7..1] – Duty Cycle Multiplier: These bits are the decimal value used to calculate the Duty Cycle or “On time” of the Receiver after the wake-up timer has brought the TRC102 out of sleep mode. Bit [0] – Duty Cycle Mode Enable: This bit enables the duty cycle mode when set. ...

Page 40

... Email: info@rfm.com ©by RF Monolithics, Inc. [POR=C000h] Bit Bit Bit Bit Bit CLK2 CLK1 CLK0 TABLE 16. CLK2 CLK1 1 0 1. 2 Bit Bit Bit Bit Bit LBD3 LBD2 LBD1 LBD0 CLK0 Page TRC102 - 4/8/08 0 ...

Page 41

... Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC102 - 4/8/08 ...

Page 42

... BUF1 BUF0 Table 17. Freq BUF1 BUF0 >5 MHz MHz 0 1 <2.5 MHz 1 X Table 18. Time Current XSU 1ms 620uA 460uA 1 Table 19. Phase Noise -107 dBc/Hz -102 dBc/Hz Bit Bit Bit Bit Bit XSU PDD DITH 1 PLLBW PLLBW 0 1 Page TRC102 - 4/8/08 ...

Page 43

... Band mA 868MHz Band 916MHz Band 433MHz Band mA 868MHz Band 916MHz Band 433MHz Band mA 868MHz Band 916MHz Band Unit Test Conditions max 0.3*Vdd µA Vil = µA Vih = Vdd, Vdd = 5.4 V 0.4 V Iol = Ioh = - Load = 15 pF Page TRC102 - 4/8/ °C ° °C ...

Page 44

... Analog filter kHz Δdev = FSK deviation pF pF 350 mV 1000 mV Ohm dB LNA Gain = max, dB RFin<-60dBm dBm RSSI signal goes high after input signal exceeds us programmed limit. CAPARRSI = 1pF 433 MHz Band dBm 868 MHz Band 916 MHz Band Page TRC102 - 4/8/08 ...

Page 45

... Band dBm 868MHz Band 916MHz Band 433MHz Band dBm 868MHz Band 916MHz Band All Bands dBc All Bands 433MHz Band pF 868MHz Band 916MHz Band 433MHz Band 868MHz Band 916MHz Band 100 kHz from carrier dBc/Hz 1 MHz from carrier Page TRC102 - 4/8/08 ...

Page 46

... Vdd at 90% of final value ms Calibrated every 30 seconds Unit Test Conditions MHz us within 1kHz settle, 10MHz step us Crystal running Programmable in 0.5 pF steps, pF tolerance +/- 10% ms Crystal ESR < 100 Ohms 433MHz Band (2.5kHz steps) MHz 868MHz Band (5.0kHz steps) 916MHz Band (7.5kHz steps) Page TRC102 - 4/8/08 ...

Page 47

... Email: info@rfm.com ©by RF Monolithics, Inc. -3 BER. Sensitivity vs Data Rate 915MHz 868MHz 4800 9600 19200 Data Rate (bps) Sensitivity vs Receive Bandwidth 433MHz 915MHz 200 Bandwidth (kHz) 38400 57600 115000 405 Page TRC102 - 4/8/08 ...

Page 48

... Receive Current vs Voltage (2.4kbps) 14.0 13.0 12.0 11.0 10.0 2.2 www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. 915MHz 868MHz 433MHz 3 3.8 Voltage (V) Page TRC102 - 4/8/08 ...

Page 49

... Current vs Operating Voltage (Max Output Power) 25.0 24.0 23.0 22.0 21.0 20.0 2.2 www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Voltage vs Output Power 3 Voltage (V) 3 Voltage (V) 433MHz 868MHz 915MHz 3.8 915MHz 868MHz 433MHz 3.8 Page TRC102 - 4/8/08 ...

Page 50

... IPC/JEDEC J-STD-020C REFLOW PROFILE www.RFM.com Email: info@rfm.com ©by RF Monolithics, Inc. Page TRC102 - 4/8/08 ...

Page 51

... BSC. 0.19 0.30 0.007 0.65 BSC. 0.026 BSC. 0.80 0.90 1.05 0.031 0.035 1.20 0.50 0.60 0.75 0.020 0.024 1.00 REF. 0.39 REF 0.09 0.004 0.09 0.004 REF. 12 REF. 12 REF. 12 REF. Page TRC102 - 4/8/08 Max 0.177 0.201 0.012 0.041 0.47 0.030 8 ...

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