ATA8742-PXQW Atmel, ATA8742-PXQW Datasheet - Page 139

• Manufacturer Part Number: ATA8742-PXQW
• Description: MCU W/TRANSMITTER ASK/FSK 24QFN
• Manufacturer: Atmel

Specifications of ATA8742-PXQW

• Frequency: 433MHz
• Applications: Home Automation, Remote Sensing, RKE
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 32 kBit/s
• Power - Output: 7.5dBm
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 8.1 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATASTK512-EK1-IND
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

23.3
23.3.1
9151A–INDCO–07/09
Functional Descriptions
Three-wire Mode
The 4-bit counter can be both read and written via the data bus, and can generate an overflow
interrupt. Both the Serial Register and the counter are clocked simultaneously by the same clock
source. This allows the counter to count the number of bits received or transmitted and generate
an interrupt when the transfer is complete. Note that when an external clock source is selected
the counter counts both clock edges. In this case the counter counts the number of edges, and
not the number of bits. The clock can be selected from three different sources: The USCK pin,
Timer/Counter0 Compare Match or from software.
The Two-wire clock control unit can generate an interrupt when a start condition is detected on
the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con-
dition is detected, or after the counter overflows.
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but
does not have the slave select (SS) pin functionality. However, this feature can be implemented
in software if necessary. Pin names used by this mode are: DI, DO, and USCK.
Figure 23-2. Three-wire Mode Operation, Simplified Diagram
Figure 23-2 on page 139
one as Slave. The two Shift Registers are interconnected in such way that after eight USCK
clocks, the data in each register are interchanged. The same clock also increments the USI’s
4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to deter-
mine when a transfer is completed. The clock is generated by the Master device software by
toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR.
SLAVE
MASTER
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
shows two USI units operating in Three-wire mode, one as Master and
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
PORTxn
USCK
USCK
DO
DO
DI
DI
ATA8742
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