ATA8742-PXQW Atmel, ATA8742-PXQW Datasheet - Page 177

MCU W/TRANSMITTER ASK/FSK 24QFN

ATA8742-PXQW

Manufacturer Part Number
ATA8742-PXQW
Description
MCU W/TRANSMITTER ASK/FSK 24QFN
Manufacturer
Atmel
Datasheet

Specifications of ATA8742-PXQW

Frequency
433MHz
Applications
Home Automation, Remote Sensing, RKE
Modulation Or Protocol
ASK, FSK
Data Rate - Maximum
32 kBit/s
Power - Output
7.5dBm
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Voltage - Supply
2 V ~ 4 V
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA8x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
8.1 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ATASTK512-EK1-IND
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATA8742-PXQW
Manufacturer:
ATMEL
Quantity:
1 482
27.1.1
27.1.2
27.1.3
9151A–INDCO–07/09
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
Preventing Flash Corruption
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruction
is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR, the
value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits will
auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within
three CPU cycles or no SPM instruction is executed within four CPU cycles. When RFLB and
SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and
SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the
RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be
loaded in the destination register as shown below. See
description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-
tion is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the
value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. See
Table 28-4 on page 181
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Bit
Rd
Bit
Rd
Bit
Rd
FHB7
FLB7
7
7
7
CC
for detailed description and mapping of the Fuse High byte.
FLB6
FHB6
, the Flash program can be corrupted because the supply voltage is
6
6
6
FHB5
FLB5
5
5
5
FHB4
FLB4
4
4
4
FLB3
FHB3
3
3
3
Table 28-5 on page 182
FHB2
FLB2
2
2
2
FHB1
FLB1
LB2
1
1
1
ATA8742
FLB0
FHB0
LB1
0
0
0
for a detailed
177

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