ATA8742-PXQW Atmel, ATA8742-PXQW Datasheet - Page 53

• Manufacturer Part Number: ATA8742-PXQW
• Description: MCU W/TRANSMITTER ASK/FSK 24QFN
• Manufacturer: Atmel

Specifications of ATA8742-PXQW

• Frequency: 433MHz
• Applications: Home Automation, Remote Sensing, RKE
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 32 kBit/s
• Power - Output: 7.5dBm
• Current - Transmitting: 9.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 4kB Flash, 256B EEPROM, 256B SRAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Processor Series: ATA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 4 KB
• Data Ram Size: 256 B
• Interface Type: SPI, USI
• Maximum Clock Frequency: 8.1 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ATASTK512-EK1-IND
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

15.8
15.8.1
9151A–INDCO–07/09
Register Description
MCUCR – MCU Control Register
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. See the section
which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an
analog signal level close to V
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to V
input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). See
“DIDR0 – Digital Input Disable Register 0” on page 172
The MCU Control Register contains control bits for power management.
• Bit 5 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
• Bits 4, 3 – SM1..0: Sleep Mode Select Bits 2..0
These bits select between the three available sleep modes as shown in
Table 15-2.
Note:
• Bit 2 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny24/44/84 and will always read as zero.
Bit
Read/Write
Initial Value
SM1
1. Only recommended with external crystal or resonator selected as clock source
0
0
1
1
Sleep Mode Select
CC
R
7
–
0
/2 on an input pin can cause significant current even in active mode. Digital
PUD
R/W
SM0
6
0
0
1
0
1
“Digital Input Enable and Sleep Modes” on page 76
CC
/2, the input buffer will use excessive power.
R/W
SE
5
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Standby
SM1
R/W
4
0
(1)
SM0
R/W
3
0
for details.
—
R
2
0
ISC01
R/W
1
0
Table 15-2 on page
ATA8742
ISC00
R/W
0
0
for details on
MCUCR
53.
53