ATA8743-PXQW Atmel, ATA8743-PXQW Datasheet
ATA8743-PXQW
Specifications of ATA8743-PXQW
Related parts for ATA8743-PXQW
ATA8743-PXQW Summary of contents
Page 1
... Its primary appli- cations are in the areas of industrial/aftermarket Remote Keyless-Entry (RKE) systems, alarm, telemetering, energy metering systems, home automotion/entertain- ment and toys. The ATA8743 can be used in the frequency band of f ASK or FSK data transmission. ® ...
Page 2
... UHF ASK/FSK Remote Control Transmitter ATA8743 S1 ATtiny44V PXY S1 PXY S1 PXY PXY PXY PXY PXY ATA8403 Power up/down f/4 PLL CLK XTO VCO PA ATA8743 2 VDD VS GND PXY PXY PXY PXY PXY ENABLE ATA8205 GND_RF VCC_RF VS Antenna PA_ENABLE ANT2 Loop Antenna LNA ANT1 VS ...
Page 3
... Power up/down f/4 PLL CLK XTO VCO PA 9152B–INDCO–02/10 VDD VS GND PXY PXY PXY PXY PXY ENABLE ATA8205 GND_RF VCC_RF VS Antenna PA_ENABLE ANT2 Loop Antenna ANT1 LNA VS ATA8743 UHF ASK/FSK Remote Control Receiver Demod Control PLL XTO VCO Micro- controller 3 ...
Page 4
... Port 4-bit bi-directional I/O port with internal pull-up resistor 19 GND Microcontroller ground 20 XTAL Connection for crystal 21 VS_RF Transmitter supply voltage 22 GND_RF Transmitter ground 23 ENABLE Enable input 24 GND Ground GND Ground/backplane (exposed die pad) ATA8743 VCC 1 18 PB0 2 17 PB1 3 16 PB3/RESET 4 15 PB2 ...
Page 5
... Switches on power amplifier. 9 PA_ENABLE Used for ASK modulation 10 ANT2 Emitter of antenna output stage. 11 ANT1 Open collector antenna output. 20 XTAL Connection for crystal. 9152B–INDCO–02/10 Configuration /4 XTAL ATA8743 VS 100 CLK 100 50 k PA_ENABLE U 20 µA ANT1 ANT2 VS VS 1.5 k 1.2 k XTAL 182 µ ...
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... Table 2-2. Pin Description (Continued) Pin Symbol Function 21 VS Supply voltage 22 GND Ground 23 ENABLE Enable input ATA8743 6 Configuration See ESD protection circuitry (see Figure 8-1 on page See ESD protection circuitry (see Figure 8-1 on page ENABLE 200 k 12). 12). 9152B–INDCO–02/10 ...
Page 7
... With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver, and the power amplifier are on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform the ASK modulation. 9152B–INDCO–02/10 Figure 1-1 on page 2 and Figure 1-2 on page ATA8743 3). The CLK line is used to allow the 7 ...
Page 8
... The switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the fol- lowing tolerances are considered. Figure 3-1. ATA8743 8 f hence a 13.5672 MHz crystal is needed for a 868.3 MHz transmitter and a ...
Page 9
... Switch = ±10%, a parallel capacitance of the Stray2 = 13 fF ±10%, an FSK deviation of ±21.5 kHz M = (166 + j226) at 868.3 MHz. There must be a low is achieved for the maximum output Figure 8-4 on page = (166 + j226) at 868.3 MHz. In addition, the Load,opt ATA8743 ® ’s AVR 16. Note 9 ...
Page 10
... Load capacitance at pin CLK = 10 pF Spurious emission f f other spurious are lower f f Oscillator frequency XTO C (= phase comparator frequency) accordingly T PLL loop bandwidth Note higher than 3.6V, the maximum voltage will be reduced to 3.6V. S ATA8743 10 Symbol tot stg T amb V maxPA_ENABLE Symbol R thJA = 25° ...
Page 11
... High level input voltage Input current high Note higher than 3.6V, the maximum voltage will be reduced to 3.6V. S 9152B–INDCO–02/10 = 25°C. All parameters are referred to GND (pin 7). amb = f PC XT0 Load ATA8743 Symbol Min. Typ. Max. –116 –110 –80 –74 –89 –86 –120 –117 f ...
Page 12
... 100 nH) can be printed on PCB the load resonance frequency of the crystal. Normally, a value results for load-capacitance crystal. Figure 8-1. ATA8743 12 two capacitors in series should be used to achieve a better tolerance 2 st harmonic, hence the position placed as close as possible to the pins ANT1 and 1 ...
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... Figure 8-2. VCC Table 8-1. Bill of Material Component 315 MHz 433.92 MHz L1 100 3 3 100 nF 100 nF 9152B–INDCO–02/10 Typical ASK Application ATA8743 VDD C7 2 PB0/XTAL1 PB1/XTAL2 ATA874x 4 PB3/RESET 5 PB2 6 PA7 ADC7 Type/ Value Manufacturer Note 868.3 MHz LL1608-FSL TOKO LL1608-FSL ...
Page 14
... Note: ATA8743 14 Type/ Value Manufacturer Note GRM188R71C / 100 nF Murata GRM1885C Murata DSX530GK/ 13.567187 MHz 100 k 100 k 100 k 100 1.8 k 1.8 k Typical FSK Application ATA8743 VDD 2 C7 PB0/XTAL1 PB1/XTAL2 4 PB3/RESET 5 PB2 6 PA7 ADC7 FSK Modulation is Achieved by Switching on/off an Additional Capacitor Between the XTAL Load Capacitor and GND ...
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... This cap must placed as close as possible to the VCC_RF This cap must placed as close as possible to the VDD Frequency deviation of ±16 kHz will be performed using the combination of C8 and C9 Frequency deviation of ±16 kHz will be performed using the combination of C8 and C9 KDS ATA8743 15 ...
Page 16
... ANT2 ANT1 XTAL VS GND ENABLE For the ATA8743, the following points differs from the datasheets: - The temperature range is limited to –40°C to +85°C - ESD protection: HBM 2500V, MM 100V, CDM 1000V - Figure 8-4 on page 16: Two output power measurement - For FSK modulation, an additional MOS switch is required ...
Page 17
... PA5/MISO PA4/USCK PA3/T0 PA2 PA1 PA0 GND For the ATA8741/ATA8742/ATA8743, the following points differs from the ATtiny44V data sheet: - The temperature range is limited to –40°C to +85°C - The supply voltage range is limited from 2.0V to 4.0V Pin Number Pin Number ATtiny44V ATA8741/ATA8742/ATA8743 ...
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... Appendix: Microcontroller ATtiny24/44/84 ATA8743 18 9152B–INDCO–02/10 ...
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... INSTRUCTION Y DECODER Z CONTROL ALU LINES STATUS REGISTER PROGRAMMING ISP INTERFACE LOGIC DATA REGISTER DATA DIR. PORT A REG.PORT A PORT A DRIVERS PA7-PA0 ATA8743 INTERNAL INTERNAL CALIBRATED OSCILLATOR OSCILLATOR WATCHDOG TIMING AND TIMER CONTROL MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1 ...
Page 20
... ATtiny24/44/84 have been verified during regular product qualifica- tion as per AEC-Q100. As indicated in the ordering information paragraph, the product is available in only one tempera- ture grade, Table 9-1. Temperature -40; +125 ATA8743 20 Temperature Grade Identification for Automotive Products Temperature Identifier Z Full Automotive Temperature Range Comments 9152B– ...
Page 21
... The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/coun- ter, SPI and pin change interrupt as described in 9152B–INDCO–02/10 ATA8743 77. Figure 16-1 on page “Alternate Port Functions” on page 77 21 ...
Page 22
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATA8743 22 9152B–INDCO–02/10 ...
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... Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. 9152B–INDCO–02/10 Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATA8743 Data Bus 8-bit Status and Control General Purpose Interrupt Registrers Unit Watchdog Timer ALU ...
Page 24
... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATA8743 24 9152B–INDCO–02/10 ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 9152B–INDCO–02/ R/W R/W R/W R ATA8743 R/W R/W R/W R SREG 25 ...
Page 26
... The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in ATA8743 26 shows the structure of the 32 general purpose working registers in the ...
Page 27
... R29 (0x1D R31 (0x1F SP15 SP14 SP13 SP12 SP7 SP6 SP5 SP4 R/W R/W R/W R/W R/W R/W R/W R ATA8743 R26 (0x1A R28 (0x1C R30 (0x1E SP11 SP10 SP9 SP8 SP3 SP2 SP1 SP0 R/W R/W R/W R/W R/W R/W R/W R/W 0 ...
Page 28
... Interrupt Vectors. The complete list of vectors is shown in determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. ATA8743 28 , directly generated from the selected clock source for the CPU ...
Page 29
... SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ 9152B–INDCO–02/10 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ATA8743 29 ...
Page 30
... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATA8743 30 ; set Global Interrupt Enable 9152B–INDCO–02/10 ...
Page 31
... The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. 9152B–INDCO–02/10 “Memory Programming” on page 180 28. Program Memory shows how the ATtiny24/44/84 SRAM Memory is organized. ATA8743 contains a detailed description on Flash “Instruction Execution Tim- 0x0000 0x03FF/0x07FF/0xFFF 31 ...
Page 32
... Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk page 32. Figure 13-3. On-chip Data SRAM Access Cycles ATA8743 32 “General Purpose Register File” on page Data Memory 0x0000 - 0x001F 32 Registers ...
Page 33
... While the device is busy programming not possible to do any other EEPROM operations. 9152B–INDCO–02/10 “Serial Downloading” on page Table 13-1 on page is likely to rise or fall slowly on Power-up/down. This causes the CC “Preventing EEPROM Corruption” on page 36 and “Split Byte Programming” on page 33 ATA8743 184. 39. A self-timing func- for details on how to avoid for 33 ...
Page 34
... The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. ATA8743 34 “Oscillator Calibration Register – OSCCAL” on ...
Page 35
... EECR = (0<<EEPM1)|(0>>EEPM0) /* Set up address and data registers */ EEARL = ucAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); The code examples are only valid for ATtiny24 and ATtiny44, using 8-bit addressing mode. ATA8743 35 ...
Page 36
... Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V be used reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. ATA8743 36 ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ...
Page 37
... General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 9152B–INDCO–02/10 ATA8743 “Register Summary” on page 228. 37 ...
Page 38
... EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 13.5.4 EECR – EEPROM Control Register Bit 0x1C (0x3C) Read/Write Initial Value ATA8743 – – ...
Page 39
... EEAR Register, the EERE bit must be written to one to trigger the 9152B–INDCO–02/10 EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4 ms Erase and Write in one operation (Atomic Operation) 1 1.8 ms Erase Only 0 1.8 ms Write Only 1 – Reserved for future use ATA8743 Table 13-1. While 39 ...
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... GPIOR2 – General Purpose I/O Register 2 Bit 0x15 (0x35) Read/Write Initial Value 13.5.6 GPIOR1 – General Purpose I/O Register 1 Bit 0x14 (0x34) Read/Write Initial Value 13.5.7 GPIOR0 – General Purpose I/O Register 0 Bit 0x13 (0x33) Read/Write Initial Value ATA8743 MSB R/W R/W R/W R ...
Page 41
... AVR Clock I/O CPU Control Unit clk clk ADC FLASH Reset Logic Source clock System Clock Prescaler Clock Multiplexer Calibrated RC Crystal Low-Frequency External Clock Oscillator Oscillator Crystal Oscillator ATA8743 Flash and RAM EEPROM Watchdog Timer Watchdog clock Watchdog Oscillator Calibrated RC Oscillator 41 ...
Page 42
... Some initial guidelines for choosing capacitors for use with crystals are given in ues given by the manufacturer should be used. ATA8743 42 Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. ...
Page 43
... Crystal Oscillator Operating Modes Frequency Range (MHz) (1) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8 This option should not be used with crystals, only with ceramic resonators. 44. ATA8743 XTAL2 XTAL1 GND Table 14-3 on page Recommended Range for Capacitors C1 and C2 for Use with Crystals (pF) – ...
Page 44
... C1 and C2. When this oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 14-5. Table 14-5. SUT1.. Notes: ATA8743 44 Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and SUT1..0 Power-save (1) 00 258 CK (1) ...
Page 45
... Calibration Register – OSCCAL” on Table 29-2 on page 182. Nominal Frequency 8.0 MHz Additional Delay from Reset (V = 5.0V) Recommended Usage CC 14CK BOD enabled 14CK + 4 ms Fast rising power 14CK + 64 ms Slowly rising power Reserved ATA8743 Table 29-2 for more details. Table 197. Figure 45 ...
Page 46
... It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. See to 47 for details. ATA8743 46 EXTERNAL CLOCK SIGNAL 46. ...
Page 47
... Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Additional Delay from Power-down and Power-save Table 14-10 on page ATA8743 Reset Recommended Usage 14CK BOD enabled 14CK + 4 ms Fast rising power 14CK + 64 ms Slowly rising power Reserved ...
Page 48
... These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchro- nous peripherals is reduced when a division factor is used. The division factors are given in Table 14-10 on page ATA8743 ...
Page 49
... The device is shipped with the CKDIV8 Fuse programmed. Table 14-10. Clock Prescaler Select CLKPS3 9152B–INDCO–02/10 CLKPS2 CLKPS1 ATA8743 CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 49 ...
Page 50
... Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, ATA8743 50 presents the different clock systems in the ATtiny24/44/84, and their dis- ...
Page 51
... Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See sleep modes, the clock is already stopped. 9152B–INDCO–02/10 “PRR – Power Reduction Register” on page “Power-down Supply Current” on page 212 ATA8743 , clk , and clk I/O CPU FLASH “ ...
Page 52
... In sleep modes where both the I/O clock (clk will be disabled. This ensures that no power is consumed by the input logic when not needed. In ATA8743 52 “Analog Comparator” on page 150 “Brown-out Detection” on page 59 for details on the start-up time. “ ...
Page 53
... Sleep Mode 0 0 Idle 0 1 ADC Noise Reduction 1 0 Power-down 1 1 Standby 1. Only recommended with external crystal or resonator selected as clock source for details SM1 SM0 — ISC01 R/W R Table 15-2 on page (1) ATA8743 for details on 0 ISC00 MCUCR R/W 0 53. 53 ...
Page 54
... USI again, the USI should be re initialized to ensure proper operation. • Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. ATA8743 ...
Page 55
... Brown-out Reset. The MCU is reset when the supply voltage V threshold (V 9152B–INDCO–02/10 Figure 16-1 on page 56 defines the electrical parameters of the reset circuitry. ). POT ) and the Brown-out Detector is enabled. BOT ATA8743 shows the reset logic. Table 16-1 on “Clock Sources” on page 42. is below the Brown-out Reset CC 55 ...
Page 56
... A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V Figure 16-2. MCU Start-up, RESET Tied TIME-OUT INTERNAL ATA8743 56 Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor SPIKE FILTER ...
Page 57
... Power-on Reset signal VCC Min. start voltage to ensure internal Power-on Reset signal VCC Rise Rate to ensure Power-on Reset RESET Pin Threshold Voltage 1. Before rising, the supply has to be between “System and Reset Characterizations” on page ATA8743 V RST t TOUT Min Typ 1.1 1 ...
Page 58
... Figure 16-4. External Reset During Operation ATA8743 58 CC 9152B–INDCO–02/10 ...
Page 59
... RESET TIME-OUT INTERNAL RESET for details on operation of the Watchdog Timer increases above the CC 59), the delay counter starts the MCU after the if the voltage stays below the trigger level for lon- CC 198. V BOT+ t TOUT ATA8743 level CC = BOT+ in Figure BOT- . See TOUT 59 ...
Page 60
... Sequences for Changing the Configuration of the Watchdog Timer” on page 61 Table 16-2. WDTON Unprogrammed Programmed ATA8743 60 “System and Reset Characterizations” on page 64. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The WDT Configuration as a Function of the Fuse Settings of WDTON ...
Page 61
... Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 9152B–INDCO–02/10 WATCHDOG 128 kHz PRESCALER OSCILLATOR WATCHDOG RESET WDP0 WDP1 WDP2 WDP3 WDE MCU RESET ATA8743 61 ...
Page 62
... Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs. If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared, ATA8743 ...
Page 63
... To avoid this situation, the application software should always clear the WDRF flag and the WDE control bit in the initialization routine. 64. ATA8743 Action on Time-out None Interrupt ...
Page 64
... Table 16-4. WDP3 ATA8743 64 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 Typical Time-out at Cycles cycles cycles cycles 64 ms 16K cycles 0.125 s 32K cycles 0.25 s 64K cycles 0.5 s 128K cycles 1.0 s 256K cycles 2.0 s 512K cycles 4.0 s 1024K cycles 8 ...
Page 65
... Turn off WDT ldi r16, (0<<WDE) out WDTCR, r16 ret (1) _WDR(); /* Clear WDRF in MCUSR */ MCUSR = 0x00 /* Write logical one to WDCE and WDE */ WDTCR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; 1. See “About Code Examples” on page ATA8743 22. 65 ...
Page 66
... If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny24/44/84 is: ATA8743 66 Reset and Interrupt Vectors Program Address ...
Page 67
... SPH,r16 ldi r16, low(RAMEND) out SPL,r16 sei <instr> xxx ... ... ... ATA8743 Comments ; Reset Handler ; IRQ0 Handler ; PCINT0 Handler ; PCINT1 Handler ; Watchdog Interrupt Handler ; Timer1 Capture Handler ; Timer1 Compare A Handler ; Timer1 Compare B Handler ; Timer1 Overflow Handler ; Timer0 Compare A Handler ; Timer0 Compare B Handler ...
Page 68
... The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 18.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Timing of pin change interrupts ATA8743 68 “Clock Systems and their Distribution” on page 41. pin_lat pcint_in_(0) PCINT(0) ...
Page 69
... The low level of INT0 generates an interrupt request. 1 Any logical change on INT0 generates an interrupt request. 0 The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request – INT0 PCIE1 PCIE0 R R/W R/W R ATA8743 SM0 – ISC01 ISC00 R/W R R/W R – – ...
Page 70
... These bits are reserved bits in the ATtiny24/44/84 and will always read as zero. • Bits 3..0 – PCINT11..8: Pin Change Enable Mask 11..8 Each PCINT11..8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT11..8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on ATA8743 ...
Page 71
... If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 9152B–INDCO–02/ PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATA8743 PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCMSK0 71 ...
Page 72
... Using the I/O port as General Digital I/O is described in 73. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in Functions” on page nate functions. ATA8743 72 and Ground as indicated in CC for a complete list of parameters. ...
Page 73
... D 0 PORTxn Q CLR RESET WRx RRx RPx PINxn Q Q clk I/O WDx: WRITE DDRx RDx: READ DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER 86, the DDxn bits are ATA8743 shows a func- WPx , I/O 73 ...
Page 74
... This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. page 75 value. The maximum and minimum propagation delays are denoted t respectively. ATA8743 74 summarizes the control signals for the pin value. Port Pin Configurations PUD ...
Page 75
... SYNC LATCH PINxn r17 Figure 19-4 on page 75. The out instruction sets the “SYNC LATCH” signal at the SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATA8743 XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx 0x00 ...
Page 76
... Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. ATA8743 76 (1) ... ...
Page 77
... AVR microcon- troller family. 9152B–INDCO–02/10 or GND is not recommended, since this may cause excessive currents if the pin is CC shows how the port pin control signals from the simplified ATA8743 Figure 19-5 on Figure 19-2 on page 73 can 77 ...
Page 78
... DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: Table 19-2 on page 79 indexes from signals are generated internally in the modules having the alternate function. ATA8743 78 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn ...
Page 79
... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/Output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used Input/Output bi-directionally. ATA8743 79 ...
Page 80
... AREF pin by setting (one) the bit REFS0 in the ADC Multiplexer Selection Register (ADMUX). PCINT0: Pin Change Interrupt source 0. The PA0 pin can serve as an external interrupt source for pin change interrupt 0. ATA8743 80 Port A Pins Alternate Functions Port Pin Alternate Function ADC0: ADC input channel 0 ...
Page 81
... The OC1B pin is also the output pin for the PWM mode timer function. PCINT5: Pin Change Interrupt source 5. The PA5 pin can serve as an external interrupt source for pin change interrupt 0. 9152B–INDCO–02/10 ATA8743 . . . . . ...
Page 82
... Table 19-4 on page 82 overriding signals shown in Table 19-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATA8743 82 to Table 19-6 on page 83 Figure 19-5 on page Overriding Signals for Alternate Functions in PA7..PA5 PA7/ADC7/OC0B/ICP1/ PA6/ADC6/DI/SDA/OC1A/ PCINT7 PCINT6 USIWM1 0 (SDA + PORTA6) • ...
Page 83
... ADC4 Input ADC3 Input Overriding Signals for Alternate Functions in PA1..PA0 PA1/ADC1/AIN0/PCINT1 PCINT1 • PCIE0 + ADC1D PCINT1 • PCIE0 PCINT1 Input ADC1/Analog Comparator Positive Input ATA8743 PA2/ADC2/AIN1/PCINT2 PCINT2 • PCIE + ADC2D PCINT3 • PCIE0 PCINT0 Input ADC2/Analog Comparator Negative Input PA0/ADC0/AREF/PCINT0 RESET • ...
Page 84
... CKOUT Fuse is programmed, regardless of the PORTB2 and DDB2 settings. It will also be output during reset. PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interrupt source for pin change interrupt 1. ATA8743 84 Port B Pins Alternate Functions Port Pin Alternate Function XTAL1: Crystal Oscillator Input ...
Page 85
... PCINT11 • PCIE1 (2) DEBUGWIRE_ENABLE + (RSTDISBL PCINT11 • PCIE1) dW/PCINT11 Input RSTDISBL is 1 when the Fuse is “0” (Programmed). DebugWIRE is enabled when DWEN Fuse is programmed and Lock bits are unprogrammed. ATA8743 relate the alternate functions of Port B to the 78. PB2/INT0/OC0A/CKOUT/PCINT10 (2) CKOUT 0 (2) CKOUT ...
Page 86
... Table 19-9. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 1. 2. ATA8743 86 Overriding Signals for Alternate Functions in PB1..PB0 PB1/XTAL2/PCINT9 (1) EXT_OSC 0 (1) EXT_OSC 0 (1) EXT_OSC 0 0 (1) EXT_OSC + PCINT9 • PCIE1 (1) EXT_OSC • PCINT9 • PCIE1 PCINT9 Input XTAL2 EXT_OSC = crystal oscillator or low frequency crystal oscillator is selected as system clock ...
Page 87
... DDA7 DDA6 DDA5 DDA4 R/W R/W R/W R PINA7 PINA6 PINA5 PINA4 R/W R/W R/W R N/A N – – – – ATA8743 SM0 – ISC01 ISC00 R PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 R/W R/W R/W R PINA3 PINA2 PINA1 ...
Page 88
... PINB – Port BInput Pins Address Bit 0x16 (0x36) Read/Write Initial Value ATA8743 – – N/A N PINB3 PINB2 PINB1 PINB0 R/W R/W R/W R/W N/A N/A N/A N/A 9152B–INDCO–02/10 PINB ...
Page 89
... Count Clear Control Logic Direction clk Tn TOP BOTTOM Timer/Counter TCNTn = = 0 = OCRnA Fixed TOP Value = OCRnB TCCRnA TCCRnB ATA8743 Figure 20-1 on page 89. For “Register TOVn (Int.Req.) Clock Select Edge Tn Detector ( From Prescaler ) OCnA (Int.Req.) Waveform OCnA Generation OCnB (Int.Req.) Waveform OCnB Generation 89 ...
Page 90
... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 20-2 on page 90 Figure 20-2. Counter Unit Block Diagram ATA8743 90 “Output Compare Unit” on page 91 Table 20-1 on page 90 are also used extensively throughout the document. Definitions The counter reaches the BOTTOM when it becomes 0x00 ...
Page 91
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 94. shows a block diagram of the Output Compare unit. ATA8743 in the following. T0 “Modes of Opera- “Modes of Operation” on page 94. 91 ...
Page 92
... TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform ATA8743 92 DATA BUS OCRnx ...
Page 93
... Note that some COM0x1:0 bit settings are reserved for certain modes of operation, see 9152B–INDCO–02/10 COMnx1 Waveform COMnx0 D Generator FOCn OCnx D PORT D DDR clk I/O “Register Description” on page 100 ATA8743 Figure 20-4 on page OCn Pin shows a 93 ...
Page 94
... The timing diagram for the CTC mode is shown in (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then coun- ter (TCNT0) is cleared. ATA8743 94 Table 20-2 on page 100, and for phase correct PWM refer to “ ...
Page 95
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 9152B–INDCO–02/ clk_I ------------------------------------------------------ - OCnx N OCRnx ATA8743 OCnx Interrupt Flag Set (COMnx1 clk_I/O 95 ...
Page 96
... A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of ATA8743 96 Figure 20-6 on page 96. The TCNT0 value is in the timing diagram ...
Page 97
... OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to 9152B–INDCO–02/10 97. The TCNT0 value is in the timing diagram shown as a histogram for 1 2 ATA8743 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 (COMnx1 ...
Page 98
... The figure shows the count sequence close to the MAX value in all modes other than phase cor- rect PWM mode. Figure 20-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 20-9 on page 99 ATA8743 98 Table 20-4 on page f OCnxPCPWM Figure 20-7 on page 97 Figure 20-8 on page 98 contains timing data for basic Timer/Counter operation. I/O ...
Page 99
... OCF0B in all modes and OCF0A in all modes I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP ATA8743 BOTTOM + 1 /8) clk_I/O OCRnx + 2 BOTTOM + 1 99 ...
Page 100
... WGM02:0 bit setting. WGM02:0 bits are set to a normal or CTC mode (non-PWM). Table 20-2. COM01 Table 20-3 on page 100 to fast PWM mode. Table 20-3. COM01 Note: ATA8743 100 COM0A1 COM0A0 COM0B1 R/W R/W R Table 20-2 on page 100 Compare Output Mode, non-PWM Mode COM00 ...
Page 101
... Compare Output Mode, Fast PWM Mode COM00 Description 0 Normal port operation, OC0B disconnected. 1 Reserved Clear OC0B on Compare Match, set OC0B at BOTTOM 0 (non-inverting mode) Set OC0B on Compare Match, clear OC0B at BOTTOM 1 (inverting mode) ATA8743 (1) “Phase Correct PWM Mode” on shows the COM0A1:0 bit functionality when the (1) 101 ...
Page 102
... Note: ATA8743 102 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See page 95 for more details. shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor- ...
Page 103
... Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. 9152B–INDCO–02/ FOC0A FOC0B – – “TCCR0A – Timer/Counter Control Register A” on page ATA8743 WGM02 CS02 CS01 CS00 R/W R/W R/W R 100. TCCR0B 103 ...
Page 104
... Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. ATA8743 104 Clock Select Bit Description CS01 CS00 Description ...
Page 105
... When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. 9152B–INDCO–02/ – – – – – – – – ATA8743 – OCIE0B OCIE0A TOIE0 R R/W R/W R – OCF0B OCF0A TOV0 R R/W R/W R TIMSK0 TIFR0 ...
Page 106
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. See and “Waveform Generation Mode Bit Description” on page ATA8743 106 Table 20-8 on page 102 102. 9152B–INDCO–02/10 ...
Page 107
... I/O pins. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Description” on page 9152B–INDCO–02/10 129. ATA8743 Figure 21-1 on page 108. For “Register 107 ...
Page 108
... The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See put Compare Units” on page Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. ATA8743 108 Count Clear ...
Page 109
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assignment is dependent of the mode of operation. ATA8743 109 ...
Page 110
... Therefore, when both the ATA8743 110 (1) ... ...
Page 111
... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “About Code Examples” on page ATA8743 22. 111 ...
Page 112
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources and prescaler, see ATA8743 112 (1) ; Save global interrupt flag in r18,SREG ...
Page 113
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM “Modes of Operation” on page 119. ATA8743 Tn 113 ...
Page 114
... When the CPU reads the ICR1H I/O location it will access the TEMP Register. The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera- ATA8743 114 DATA BUS TEMP (8-bit) ...
Page 115
... Changing the edge sensing must be done as early as possible after the ICR1 Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be 9152B–INDCO–02/10 110. “Accessing 16-bit Registers” (Figure 22-1 on page 136). The edge detector is also ATA8743 115 ...
Page 116
... For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com- pare Register to either TOP or BOTTOM of the counting sequence. The synchronization ATA8743 116 (“Modes of Operation” on page 119). shows a block diagram of the Output Compare unit. The small “ ...
Page 117
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 9152B–INDCO–02/10 110. ATA8743 “Accessing 16-bit Registers” 117 ...
Page 118
... The design of the Output Compare pin logic allows initialization of the OC1x state before the out- put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See The COM1x1:0 bits have no effect on the Input Capture unit. ATA8743 118 Waveform Generator I/O for details ...
Page 119
... It also simplifies the opera- tion of counting external events. 9152B–INDCO–02/10 Table 21-1 on page (“Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page ATA8743 129. For fast PWM mode refer to 118) Table 21-2 on Table 21-3 on 126. ...
Page 120
... BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x, and set at BOTTOM. In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase cor- ATA8743 120 when OCR1A is set to zero (0x0000) ...
Page 121
... The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low 9152B–INDCO–02/10 TOP log R = ---------------------------------- - FPWM log ATA8743 + 1 2 Figure 21-7 on page OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 121. ...
Page 122
... In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. ATA8743 122 Table 21-2 on page f ...
Page 123
... TOP actively while the Timer/Counter is running in the phase correct mode can 9152B–INDCO–02/10 TOP log + ---------------------------------- - PCPWM log Figure 21-8 on page 123 ATA8743 Figure 21-8 on page OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) (COMnx1 (COMnx1 illustrates, 123 ...
Page 124
... OCR1x Register is updated by the OCR1x Buffer Register, (see 21-8 on page 123 The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and ATA8743 124 f = ...
Page 125
... PFCPWM log 2 Figure 21-9 on page shows the output generated is, in contrast to the phase correct ATA8743 + 1 125. The figure shows phase and fre- OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom) ...
Page 126
... OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). ting of OCF1x. Figure 21-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling Figure 21-11 on page 127 ATA8743 126 f OCnxPFCPWM Figure 21-10 on page 126 ...
Page 127
... TCNTn TOP - 1 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value ATA8743 /8) clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 127 ...
Page 128
... Figure 21-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n ATA8743 128 clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) /8) clk_I/O TOP BOTTOM BOTTOM + 1 ...
Page 129
... Normal port operation, OC1A/OC1B disconnected. WGM13=0: Normal port operation, OC1A/OC1B disconnected. WGM13=1: Toggle OC1A on Compare Match, OC1B reserved. Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at BOTTOM (non-inverting mode) Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at BOTTOM (inverting mode) ATA8743 0 WGM10 TCCR1A R/W 0 “Fast PWM 129 ...
Page 130
... Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. ATA8743 130 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase Compare Output Mode, Phase Correct and Phase and Frequency Correct ...
Page 131
... OCR1A TOP ICR1 Immediate – – ICR1 BOTTOM OCR1A BOTTOM WGM13 WGM12 CS12 CS11 R/W R/W R/W R ATA8743 TOV1 Flag x at Set on MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX – TOP TOP 0 CS10 TCCR1B R/W 0 ...
Page 132
... FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. ATA8743 132 Figure 21-11. ...
Page 133
... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R 110 OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R “Accessing 16-bit Registers” on page ATA8743 R/W R/W R/W R “Accessing 16-bit R/W R/W R/W R R/W R/W R/W R 110. TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ...
Page 134
... TIFR1, is set. • Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page ATA8743 134 R/W ...
Page 135
... TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 9152B–INDCO–02/ – – ICIF1 – R ATA8743 – OCF1B OCF1A TOV1 R R/W R/W R Table 21-4 on page 131 for the TOV1 flag ...
Page 136
... Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- ATA8743 136 ). Alternatively, one of four taps from the prescaler can be used as a ...
Page 137
... Since the edge detector uses ExtClk clk_I/O clk I/O Clear PSR10 T0 Synchronization 1. The synchronization logic on the input pins ( TSM – – R ATA8743 clk T0 T0) is shown in Figure 22-1 on page – – – – /2.5. clk_I/O 136 ...
Page 138
... A transparent latch is inserted between the Serial Register Output and output pin, which delays the change of data output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. ATA8743 138 146 ...
Page 139
... USCK pin via the PORT Register or by writing a one to the USITC bit in USICR. 9152B–INDCO–02/10 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MASTER shows two USI units operating in Three-wire mode, one as Master and ATA8743 DO DI USCK DO DI USCK PORTxn 139 ...
Page 140
... The data bytes transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor set to Idle mode. Depending of the protocol used the slave device can now set its output to high impedance. ATA8743 140 ( Reference ) 1 ...
Page 141
... USICR,r16 ; MSB out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 ; LSB ATA8743 141 ...
Page 142
... Master is stored back into the r16 Register. Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag is set. ATA8743 142 out USICR,r17 in ...
Page 143
... Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MASTER shows two USI units operating in Two-wire mode, one as Master and ATA8743 VCC SDA SCL HOLD SCL Two-wire Clock Control Unit SDA SCL PORTxn 143 ...
Page 144
... If the Slave is not able to receive more data it does not acknowledge the data byte it has last received. When the Master does a read operation it must terminate the operation by force the acknowledge bit low after the last byte transmitted. Figure 23-6. Start Condition Detector, Logic Diagram ATA8743 144 ...
Page 145
... The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe. 9152B–INDCO–02/10 Figure 23-6 on page “Clock Systems and their Distribution” on page “USISR – USI Status Register” on page /4. This is also the maximum data transmit and CK ATA8743 144. The SDA line is delayed (in 41) must also be taken 145 ...
Page 146
... Bit 7 – USISIF: Start Condition Interrupt Flag When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag. ATA8743 146 7 6 ...
Page 147
... Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter- rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be 9152B–INDCO–02/ USISIE USIOIE USIWM1 USIWM0 R/W R/W R/W R ATA8743 USICS1 USICS0 USICLK USITC R/W R USICR 147 ...
Page 148
... USIWM1..0 and the USI operation is summarized in Table 23-1. USIWM1 Note: ATA8743 148 “USISR – USI Status Register” on page 146 Relations between USIWM1..0 and the USI Operation USIWM0 Description Outputs, clock hold, and start detector disabled. Port pins operates as 0 normal. ...
Page 149
... External, positive edge 1 0 External, negative edge 0 1 External, positive edge 1 1 External, negative edge ATA8743 4-bit Counter Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, both edges External, both edges Software clock strobe (USITC) Software clock strobe (USITC) Table 23-2 on page 149) ...
Page 150
... ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in 24-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. ATA8743 150 150. BANDGAP ...
Page 151
... Table 24-1. ACME 9152B–INDCO–02/10 Analog Comparator Multiplexed Input ADEN MUX4..0 Analog Comparator Negative Input x xx AIN1 1 xx AIN1 0 00000 ADC0 0 00001 ADC1 0 00010 ADC2 0 00011 ADC3 0 00100 ADC4 0 00101 ADC5 0 00110 ADC6 0 00111 ADC7 ATA8743 151 ...
Page 152
... Alternatively, ACI is cleared by writing a logic one to the flag. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com- parator interrupt is activated. When written logic zero, the interrupt is disabled. ATA8743 152 7 6 ...
Page 153
... Table 24-2. ACIS1/ACIS0 Settings ACIS0 Interrupt Mode 0 Comparator Interrupt on Output Toggle. 1 Reserved 0 Comparator Interrupt on Falling Output Edge. 1 Comparator Interrupt on Rising Output Edge ADC7D ADC6D ADC5D ADC4D R/W R/W R/W R ATA8743 ADC3D ADC2D ADC1D ADC0D R/W R/W R/W R DIDR0 153 ...
Page 154
... A block diagram of the ADC is shown in on page Internal reference voltage of nominally 1.1V is provided On-chip. Alternatively reference voltage for single ended channels. There is also an option to use an external volt- age reference and turn-off the internal voltage reference. ATA8743 154 ADC Input Voltage Range 155. Figure 25-1 ...
Page 155
... NEG. INPUT MUX ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS 15 ADC CTRL. & STATUS A ADC DATA REGISTER REGISTER (ADCSRA) (ADCH/ADCL) TRIGGER SELECT PRESCALER CONVERSION LOGIC SAMPLE & HOLD COMPARATOR 10-BIT DAC - + SINGLE ENDED / DIFFERENTIAL SELECTION GAIN AMPLIFIER ATA8743 0 ADC MULTIPLEXER OUTPUT 155 ...
Page 156
... Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. ATA8743 156 9152B–INDCO–02/10 ...
Page 157
... CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. 9152B–INDCO–02/10 ADTS[2:0] ADIF SOURCE EDGE DETECTOR SOURCE n ADSC ADEN Reset START CK ADPS0 ADPS1 ADPS2 PRESCALER START ADATE CONVERSION LOGIC 7-BIT ADC PRESCALER ADC CLOCK SOURCE ATA8743 CLK ADC 157 ...
Page 158
... Figure 25-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Cycle Number ADC Clock ADEN ADSC ADIF ADCH ADCL Figure 25-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL ATA8743 158 First Conversion MUX and REFS Sample & Hold ...
Page 159
... Update One Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete ADC Conversion Time Sample & Hold (Cycles from Start of Conversion) 14.5 1.5 ATA8743 One Conversion Sign and MSB of Result LSB of Result Conversion Complete Next Conversion Sign and MSB of Result LSB of Result Sample & ...
Page 160
... The reference voltage for the ADC (V ended channels that exceed V either V after switching reference voltage source may be inaccurate, and the user is advised to discard this result. ATA8743 160 REF will result in codes close to 0x3FF. V REF , or internal 1.1V reference, or external AREF pin. The first ADC conversion result CC ) indicates the conversion range for the ADC ...
Page 161
... CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed ADCn I IL ATA8743 Figure 25-8 on page /2) should not be present to avoid ADC 1..100 S 161 ...
Page 162
... Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB ATA8743 162 analog ground plane, and keep them well away from high-speed switching digital tracks ...
Page 163
... Figure 25-11. Integral Non-linearity (INL) • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. 9152B–INDCO–02/10 Output Code Output Code ATA8743 Gain Error Ideal ADC Actual ADC V ...
Page 164
... LSB. The result is presented in one-sided form, from 0x3FF to 0x000. 25.8.2 Unipolar Differential Conversion If differential channels and an unipolar input mode are used, the result is where V and V REF ATA8743 164 Output Code 0x3FF 1 LSB 0x000 0 ADC ...
Page 165
... Table 25-2 on page 165 T = {[(ADCH << ADCL] - TOS 512 – NEG GAIN V REF the voltage on the negative input pin, NEG C after offset calibration. Band- 10° +85°C 380 mV are typical values. However, due to the process is the temperature sen- OS ATA8743 +125°C 424 mV 165 ...
Page 166
... Selections on page 167 the offset calibration selections are located. Selecting the single-ended channel ADC8 enables the temperature measurement. See changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set). ATA8743 166 REFS1 ...
Page 167
... Operation” on page 155 MUX5..0 000000 000001 000010 000011 000100 000101 000110 000111 (1) 001000 - 011111 100000 100001 100010 (3) 100011 - 100111 (1) 101000 - 111111 and “ADC Operation” on page 155 168. When MUX0 bit is cleared (‘0’) 1x gain is describes offset calibration in a more ATA8743 167 ...
Page 168
... Table 25-5. Positive Differential ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) ADC4 (PA4 ADC5 (PA5) ADC6 (PA6) ADC7 (PA7) 1. ATA8743 168 Differential Input channel Selections. Negative Differential Input Input (1) ADC0 (PA0) ADC1 (PA1) ADC3 (PA3) ADC0 (PA0) ADC2 (PA2) ADC3 (PA3) ...
Page 169
... These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 25-6. ADPS2 9152B–INDCO–02/ ADEN ADSC ADATE R/W R/W R ADC Prescaler Selections ADPS1 ADIF ADIE ADPS2 ADPS1 R/W R/W R/W R ADPS0 Division Factor ATA8743 0 ADPS0 ADCSRA R 169 ...
Page 170
... The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in page 164. ATA8743 170 ADC Prescaler Selections (Continued) ADPS1 ...
Page 171
... ADC Auto Trigger Source Selections ADTS1 ADLAR – ADTS2 ADTS1 R/W R/W R/W R 152. “ADCL and ADCH – ADC Data Register” on ADTS0 Trigger Source 0 Free Running mode 1 Analog Comparator 0 External Interrupt Request 0 1 Timer/Counter0 Compare Match A 0 Timer/Counter0 Overflow ATA8743 0 ADTS0 ADCSRB R 171 ...
Page 172
... The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. ATA8743 172 ADC Auto Trigger Source Selections ...
Page 173
... Figure 26-1 on page 173 the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. 9152B–INDCO–02/10 VCC dW dW(RESET) GND shows the schematic of a target MCU, with debugWIRE enabled, and ATA8743 1.8 - 5.5V 173 ...
Page 174
... Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATA8743 174 will not work. CC ® ...
Page 175
... SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 9152B–INDCO–02/10 ATA8743 175 ...
Page 176
... Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 27-1. Addressing the Flash During SPM Z - REGISTER Note: ATA8743 176 Z15 ...
Page 177
... FLB7 FLB6 FLB5 FLB4 for detailed description and mapping of the Fuse High byte FHB7 FHB6 FHB5 FHB4 , the Flash program can be corrupted because the supply voltage is CC ATA8743 – – LB2 LB1 Table 28-5 on page 182 for a detailed FLB3 FLB2 ...
Page 178
... If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit ATA8743 178 (1) ...
Page 179
... SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect. 9152B–INDCO–02/10 ATA8743 179 ...
Page 180
... Program memory can be read out via the debugWIRE interface when the DWEN fuse is pro- grammed, even if the Lock Bits are set. Thus, when Lock Bit security is required, should always debugWIRE be disabled by clearing the DWEN fuse. Table 28-1. Lock Bit Byte LB2 LB1 Note: Table 28-2. LB Mode Notes: ATA8743 180 (1) Lock Bit Byte Bit ...
Page 181
... Table 28-5 on page 182 Default Value 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) Default Value 1 (unprogrammed) 1 (unprogrammed) 0 (programmed, SPI prog. enabled) 1 (unprogrammed) 1 (unprogrammed, EEPROM not preserved) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) for description of RSTDISBL and DWEN “Program And Data ATA8743 for 181 ...
Page 182
... Signature area of the ATtiny24/44/84 has one byte of calibration data for the internal RC Oscilla- tor. This byte resides in the high byte of address 0x000. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. ATA8743 182 Fuse Low Byte ...
Page 183
... PC[4:0] (8K bytes) No. of Words in a Page and No. of Pages in the EEPROM EEPROM Size Page Size PCWORD 128 bytes 4 bytes EEA[1:0] 256 bytes 4 bytes EEA[1:0] 512 bytes 4 bytes EEA[1:0] ATA8743 No. of Pages PCPAGE PCMSB 64 PC[9: PC[10:5] 10 128 PC[11:5] 11 No. of Pages PCPAGE EEAMSB ...
Page 184
... Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for f High: > 2 CPU clock cycles for f ATA8743 184 MOSI MISO SCK ...
Page 185
... WD_EEPROM 186 chip erased device, no 0xFFs in the data file(s) need to be programmed. WD_EEPROM 186 chip erased device, no 0xFF in the data file(s) need to be power off. CC ATA8743 Table 28-11): before WD_FLASH 186.) Accessing the serial program- Table 28-10 on ...
Page 186
... Read Extended Fuse Bits Read Calibration Byte (6) Write Instructions Write Program Memory Page Write EEPROM Memory Write EEPROM Memory Page (page access) Write Lock bits ATA8743 186 Minimum Wait Delay and Figure 28-2 on page 187 describes the Instruction set. Instruction Format Byte 1 ...
Page 187
... Program Memory/ EEPROM Memory Instruction Format Byte 2 Byte 3 $A0 $00 $A8 $00 $A4 $00 Write Program Memory Page/ Write EEPROM Memory Page Byte 1 Byte 2 Byte 3 Adr MSB Bit 15 B Page Number ATA8743 Byte4 data byte in data byte in data byte in Figure 28-2 on page Byte 4 0 187 ...
Page 188
... SII SDO SCI The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is 220 ns. Table 28-13. Pin Values Used to Enter Programming Mode Pin PA0 PA1 PA2 ATA8743 188 +11.5 - 12.5V PB3 (RESET) SCI PB0 GND Pin Name PA6 ...
Page 189
... RESET Pin High-voltage Threshold V HVRST 11.5V 11.5V 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. Table 28-15 on page ATA8743 Table 28-15 on page 192): to “000” and wait at least 100 Minimum High-voltage Period for Latching Prog_enable t HVRST ...
Page 190
... Figure 28-5. High-voltage Serial Programming Waveforms SDI MSB PB0 SII MSB PB1 SDO MSB PB2 SCI 0 1 PB3 ATA8743 190 “Page Size” on page Table 28-15 on page Figure 29-5 on page PCMSB PROGRAM PCPAGE COUNTER PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY PAGE 2 ...
Page 191
... Power-off sequence Set SCI to “0”. Set RESET to “1”. Turn V 9152B–INDCO–02/10 Table 29-8 on page Table 28-15 on page 192): 192. power off. CC ATA8743 202. When programming the Table 28-15 on page 192): Table 28-15 on page Table 28-15 on 191 ...
Page 192
... SDO x_xxxx_xxxx_xx EEPROM Page Buffer SDI 0_0000_0000_00 SII 0_0110_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0000_0000_00 Program EEPROM SII 0_0110_0100_00 Page SDO x_xxxx_xxxx_xx ATA8743 192 Instruction Format Instr.2/6 Instr.3/7 0_0000_0000_00 0_0000_0000_00 0_0110_0100_00 0_0110_1100_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx 0_eeee_eeee_00 0_0000_0000_00 0_0010_1100_00 0_0110_1101_00 x_xxxx_xxxx_xx x_xxxx_xxxx_xx 0_0000_0000_00 0_0000_0000_00 0_0111_1101_00 ...
Page 193
... ATA8743 Instr.4 Operation Remarks 0_0000_0000_00 Repeat Instr for each new 0_0110_1101_00 address. Wait after Instr. 6 until SDO goes high. See Note 3. x_xxxx_xxxx_xx Instr. 5-6 Enter EEPROM Read mode. 0_0000_0000_00 Repeat Instr ...
Page 194
... The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM. Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming. ATA8743 194 9152B–INDCO–02/10 ...
Page 195
... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Typ. Max. -0.5 0.3V CC ( ( 0.8 0.5 4.3 2 <0.05 1 <0. ATA8743 (1) Units V ( µA µ 195 ...
Page 196
... If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current greater than the listed test condition. Pull up driving strength of the PB3 RESET pad is weak. 29.2 Speed Grades Figure 29-1. Maximum Frequency vs. V 16MHz 8MHz ATA8743 196 T = -40°C to 125° 2.7V to 5.5V (unless otherwise noted Condition Min ...
Page 197
... The overall jitter increase proportionally to the divider ratio V IH1 V CC Min. 0 100 40 40 Temperature 25°C -40°C - 125°C -40°C - 125° Standard Deviation 0 2 4.5 - 5.5V CC Max. Min. Max 1.6 0.5 1.6 0 ATA8743 Accuracy ±2% ±20% (1) Units MHz µs µs % 197 ...
Page 198
... BODLEVEL [2..0] Fuses Note: 29.5 ADC Characteristics – Preliminary Data Table 29-6. ADC Characteristics, Single Ended Channels. -40°C - 125°C Symbol Parameter Resolution Absolute accuracy (Including TUE INL, DNL, quantization error, gain and offset error) ATA8743 198 Condition ( 2.7V 2.7V 2.7V ...
Page 199
... REF CC ADC clock = 200 kHz Single Ended Conversion 4V, -3.5 REF CC ADC clock = 200 kHz Free Running Conversion 65 50 2.56 GND 1.0 ATA8743 Typ Max Units 0.5 1.5 LSB 0.3 0.7 LSB -3.0 5.0 LSB 1.5 3.5 LSB 260 µs ...
Page 200
... Table 29-7. ADC Characteristics, Differential Channels, T Symbol Parameter Resolution TUE Absolute Accuracy INL Integral Non-Linearity (INL) DNL Differential Non-linearity (DNL) Gain Error ATA8743 200 = -40°C to 125°C A Condition Min Gain = 1x Gain = 20x Gain = 4V REF CC ADC clock = 50 - 200 kHz Gain = 20x V = 4V, V ...