IC MCU 1KX14 RF FSK/ASK 20SSOP

RFPIC12F675F-I/SS

Manufacturer Part NumberRFPIC12F675F-I/SS
DescriptionIC MCU 1KX14 RF FSK/ASK 20SSOP
ManufacturerMicrochip Technology
SeriesPIC®
RFPIC12F675F-I/SS datasheets
 


Specifications of RFPIC12F675F-I/SS

Package / Case20-SSOPFrequency380MHz ~ 450MHz
ApplicationsRKE, Security SystemsModulation Or ProtocolASK, FSK
Data Rate - Maximum40 kbpsPower - Output10dBm
Current - Transmitting14mAData InterfacePCB, Surface Mount
Antenna ConnectorPCB, Surface MountMemory Size1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
Voltage - Supply2V ~ 5.5VOperating Temperature-40°C ~ 125°C
Processor SeriesRFPIC12FCorePIC
Data Bus Width8 bitData Ram Size64 B
Interface TypeUSBMaximum Clock Frequency20 MHz
Number Of Programmable I/os6Number Of Timers2
Operating Supply Voltage2 V to 5.5 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTDevelopment Tools By SupplierICE2000, DV164102, AC164101, AC164103
Minimum Operating Temperature- 40 COn-chip Adc4-ch x 10-bit
Program Memory TypeFlashProgram Memory Size1.75 KB
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164103 - MODULE RCVR RFPIC 433MHZAC164101 - MODULE TRANSMITTER RFPIC 433MHZDV164102 - KIT DEV RFPICKIT KIT 1AC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
Features-Other namesQ3188156
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rfPIC12F675K/675F/675H
Data Sheet
20-Pin FLASH-Based 8-Bit
CMOS Microcontroller
with UHF ASK/FSK Transmitter
Preliminary
 2003 Microchip Technology Inc.
DS70091A

RFPIC12F675F-I/SS Summary of contents

  • Page 1

    ... Microchip Technology Inc. 20-Pin FLASH-Based 8-Bit CMOS Microcontroller with UHF ASK/FSK Transmitter Preliminary Data Sheet DS70091A ...

  • Page 2

    ... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...

  • Page 3

    ... Community gate and garage door openers • Burglar alarm systems • Building access • Low power telemetry TM ) • Meter reading • Tire pressure sensors • Wireless sensors DD = 3V) Device rfPIC12F675K rfPIC12F675F rfPIC12F675H Preliminary •1 20 GP0/CIN+/ICSPDAT 2 19 GP1/CIN-/ICSPCLK 3 18 ...

  • Page 4

    ... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. DS70091A-page 2 Preliminary  2003 Microchip Technology Inc. ...

  • Page 5

    ... Analog to Digital Converter V REF AN0 AN1 AN2 AN3 Note 1: Higher order bits are from STATUS register.  2003 Microchip Technology Inc. be considered a complementary document to this Data Sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. ...

  • Page 6

    ... Comparator input - negative — External voltage reference — Serial programming clock General purpose I/O. Individually controlled interrupt-on-change. Prog Individually enabled pull-up. — A/D Channel 0 input — Comparator input - positive — Serial Programming Data I/O — Ground reference Preliminary  2003 Microchip Technology Inc. ...

  • Page 7

    ... Stack Level 8 RESET Vector Interrupt Vector On-chip Program Memory  2003 Microchip Technology Inc. 2.2 Data Memory Organization The data memory (see Figure 2-2) is partitioned into two banks, which contain the General Purpose regis- ters and the Special Function registers. The Special Function registers are located in the first 32 locations of each bank ...

  • Page 8

    ... ADCON0 1Fh 20h General Purpose Registers 64 Bytes 5Fh 60h 7Fh Bank 0 Unimplemented data memory locations, read as '0'. 1: Not a physical register. Preliminary  2003 Microchip Technology Inc. File Address (1) Indirect addr. 80h OPTION_REG 81h 82h PCL STATUS 83h FSR 84h TRISIO ...

  • Page 9

    ... VCFG Legend: — = unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: This is not a physical register. 2: These bits are reserved and should always be maintained as ‘0’.  2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 (2) RP0 ...

  • Page 10

    ... WPU1 WPU0 --11 -111 IOC1 IOC0 --00 0000 — — VR1 VR0 0-0- 0000 0000 0000 -000 0000 WR RD ---- x000 ---- ---- xxxx xxxx ANS1 ANS0 42,63 -000 1111  2003 Microchip Technology Inc — — — — — 14 — 14 — — — — — ...

  • Page 11

    ... Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any STATUS bits. For other instructions not affecting any STATUS bits, see the “ ...

  • Page 12

    ... Section 4.4. R/W-1 R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2003 Microchip Technology Inc. ...

  • Page 13

    ... T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and should be initialized before clearing T0IF bit. Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. rfPIC12F675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

  • Page 14

    ... Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. U-0 U-0 R/W-0 U-0 CMIE — — — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary  2003 Microchip Technology Inc. U-0 R/W-0 TMR1IE — bit Bit is unknown ...

  • Page 15

    ... TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. rfPIC12F675 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

  • Page 16

    ... CAL2 CAL1 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary U-0 R/W-0 R/W-x — POR BOD bit Bit is unknown R/W-0 U-0 U-0 CAL0 — — bit Bit is unknown  2003 Microchip Technology Inc. ...

  • Page 17

    ... PCL memory boundary (each 256-byte block). Refer to the Application Note “Implementing a Table Read" (AN556).  2003 Microchip Technology Inc. 2.3.2 STACK The rfPIC12F675 Family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable ...

  • Page 18

    ... Not Used Bank 1 Bank 2 Bank 3 Preliminary INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing (1) 7 FSR Register 0 Location Select 1FFh  2003 Microchip Technology Inc. ...

  • Page 19

    ... Port pin is > Port pin is <V Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. Note: The ANSEL (9Fh) and CMCON (19h) ...

  • Page 20

    ... WPU4 — Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-x R/W-x R/W-x TRISIO2 TRISIO1 TRISIO0 bit Bit is unknown R/W-1 R/W-1 R/W-1 WPU2 WPU1 WPU0 bit Bit is unknown  2003 Microchip Technology Inc. ...

  • Page 21

    ... Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized. Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of GPIO ...

  • Page 22

    ... FIGURE 3-1: BLOCK DIAGRAM OF GP0 AND GP1 PINS Analog Input Mode Data Bus WPU RD WPU PORT TRISIO RD TRISIO RD PORT IOC RD IOC Interrupt-on-Change To Comparator To A/D Converter Preliminary  2003 Microchip Technology Inc Weak GPPU V DD I/O pin SS V Analog Input Mode PORT ...

  • Page 23

    ... IOC Q EN Interrupt-on-Change RD PORT To TMR0 To INT To A/D Converter  2003 Microchip Technology Inc. 3.3.4 GP3/MCLR/V Figure 3-3 shows the diagram for this pin. The GP3 pin is configurable to function as one of the following: • a general purpose input • as Master Clear Reset FIGURE 3-3: ...

  • Page 24

    ... Interrupt-on-Change To TMR1 or CLKGEN Note 1: Timer1 LP Oscillator enabled 2: When using Timer1 with LP oscillator, the Schmitt Trigger is by-passed. Preliminary BLOCK DIAGRAM OF GP5 INTOSC Mode (1) TMR1LPEN DD V Weak GPPU Oscillator Circuit OSC2 V DD I/O pin V SS INTOSC Mode ( PORT  2003 Microchip Technology Inc. ...

  • Page 25

    ... WPU — — 96h IOC — — 9Fh ANSEL — ADCS2 Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by GPIO.  2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 GP5 GP4 GP3 GP2 GP1 T0IE INTE ...

  • Page 26

    ... NOTES: DS70091A-page 24 Preliminary  2003 Microchip Technology Inc. ...

  • Page 27

    ... Watchdog Timer WDTE Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.  2003 Microchip Technology Inc. Counter mode is selected by setting the T0CS bit (OPTION_REG<5>). In this mode, the Timer0 module will increment either on every rising or falling edge of pin GP2/T0CKI. The incrementing edge is determined ...

  • Page 28

    ... R/W-1 R/W-1 R/W-1 T0CS T0SE PSA 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary OSC R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2003 Microchip Technology Inc. ...

  • Page 29

    ... OPTION_REG GPPU INTEDG 85h TRISIO — — Legend: — = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Timer0 module.  2003 Microchip Technology Inc. EXAMPLE 4-1: bcf STATUS,RP0 clrwdt clrf TMR0 bsf STATUS,RP0 movlw b’00101111’ ;Required if desired ...

  • Page 30

    ... Timer1 module. Note: Additional information on timer modules is available in the PICmicro Reference Manual (DS33023). 0 TMR1L 1 T1SYNC 1 Prescaler OSC /4 Internal 0 Clock 2 T1CKPS<1:0> TMR1CS Preliminary TM Mid-Range TMR1ON TMR1GE T1G TMR1ON TMR1GE Synchronized Clock Input Synchronize Detect SLEEP Input  2003 Microchip Technology Inc. ...

  • Page 31

    ... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.  2003 Microchip Technology Inc. rfPIC12F675 5.2 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit (PIR1< ...

  • Page 32

    ... Stops Timer1 Legend Readable bit - n = Value at POR DS70091A-page 30 R/W-0 R/W-0 R/W-0 OSC / Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown  2003 Microchip Technology Inc. ...

  • Page 33

    ... PIE1 EEIE ADIE Legend unknown unchanged unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.  2003 Microchip Technology Inc. 5.5 Timer1 Oscillator A crystal oscillator circuit is built-in between pins OSC1 (input) and OSC2 (amplifier output enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated kHz ...

  • Page 34

    ... NOTES: DS70091A-page 32 Preliminary  2003 Microchip Technology Inc. ...

  • Page 35

    ... CM2:CM0: Comparator Mode bits Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. be applied to an input of the comparator. In addition, GP2 can be configured as the comparator output. one analog The Comparator Control Register (CMCON), shown in Register 6-1, contains the bits to control the comparator ...

  • Page 36

    ... Table 6-1. DS70091A-page 34 TABLE 6-1: OUTPUT STATE VS. INPUT CONDITIONS Input Conditions less > < > < FIGURE 6- Output Note: CINV bit (CMCON<4>) is clear. Preliminary CINV COUT SINGLE COMPARATOR + Output –  2003 Microchip Technology Inc. ...

  • Page 37

    ... GP2/COUT Analog Input, ports always reads ‘0’ Digital Input CIS = Comparator Input Switch (CMCON<3>)  2003 Microchip Technology Inc. Comparator mode is changed, the comparator output level may not be valid for a specified period of time. Refer to the specifications in Section 13.0. Note: Comparator interrupts should be disabled during a Comparator mode change ...

  • Page 38

    ... TTL input specification. 2: Analog levels on any pin that is defined as a digital input, may cause the input buffer to consume more current than is specified CINV CMCON RESET Preliminary impedance of 10 kΩ GP0/CIN+ GP1/CIN- REF CV CM2:CM0  2003 Microchip Technology Inc. ...

  • Page 39

    ... To minimize power consumption while in SLEEP mode, turn off the comparator, CM2:CM0 = 111, and voltage reference, VRCON<7>  2003 Microchip Technology Inc. The following equations determine the output voltages: VRR = 1 (low range): CV VRR = 0 (high range): CV ...

  • Page 40

    ... Value on Value on Bit 0 all other POR, BOD RESETS 0000 0000 0000 000u GPIF 00-- 0--0 00-- 0--0 — TMR1IF -0-0 0000 -0-0 0000 CM0 00-- 0--0 00-- 0--0 — TMR1IE --11 1111 --11 1111 0-0- 0000 0-0- 0000 VR1 VR0  2003 Microchip Technology Inc. ...

  • Page 41

    ... REF applied used. The VCFG bit (ADCON0<6>)  2003 Microchip Technology Inc. The output of the sample and hold is connected to the input of the converter. The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference ...

  • Page 42

    ... ADRESL LSB Bit 0 Unimplemented: Read as ‘0’ LSB Bit 0 10-bit A/D Result  2003 Microchip Technology Inc. ...

  • Page 43

    ... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Conversion STATUS bit 1 = A/D converter module is operating 0 = A/D converter is shut-off and consumes no operating current Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. rfPIC12F675 U-0 U-0 R/W-0 R/W-0 — — CHS1 ...

  • Page 44

    ... R = Readable bit - n = Value at POR DS70091A-page 42 R/W-0 R/W-0 R/W-1 ADCS1 ADCS0 ANS3 ( Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown  2003 Microchip Technology Inc. ...

  • Page 45

    ... R = interconnect resistance SS = sampling switch C HOLD = sample/hold capacitance (from DAC)  2003 Microchip Technology Inc. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate Equation 7-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). ...

  • Page 46

    ... GPIO0 0000 0000 0000 000u INTF GPIF 00-- 0--0 00-- 0--0 — TMR1IF xxxx xxxx uuuu uuuu 00-- 0000 00-- 0000 GO ADON --11 1111 --11 1111 00-- 0--0 00-- 0--0 — TMR1IE xxxx xxxx uuuu uuuu -000 1111 -000 1111 ANS1 ANS0  2003 Microchip Technology Inc. ...

  • Page 47

    ... EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation Legend Readable bit - n = Value at POR  2003 Microchip Technology Inc. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...

  • Page 48

    ... Data EEPROM write sequence. U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-0 R/S-0 R/S-0 WREN WR RD bit Bit is unknown  2003 Microchip Technology Inc. ...

  • Page 49

    ... WREN bit clear at all times, except when updating EEPROM. The WREN bit is not cleared by hardware.  2003 Microchip Technology Inc. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set ...

  • Page 50

    ... Bit 3 Bit 2 — — CMIF — — — WRERR WREN Preliminary Value on all Value on Bit 1 Bit 0 other POR, BOD RESETS — TMR1IF 00-- 0--0 00-- 0--0 0000 0000 0000 0000 -000 0000 -000 0000 WR RD ---- x000 ---- q000 ---- ---- ---- ----  2003 Microchip Technology Inc. ...

  • Page 51

    ... There are 3 variations of this device to optimize its performance for the most commonly used frequency bands. TABLE 9-1: FREQUENCY BANDS Device Frequency rfPIC12F675K 290-350 MHz rfPIC12F675F 390-450 MHz rfPIC12F675H 850-930 MHz The internal structure of the transmitter is shown in Figure 9-1. A Colpitts oscillator reference frequency set by the attached crystal ...

  • Page 52

    ... PPM from 13.55 MHz +106 +42 -12 -24 -33 - 25°C, RFEN = 1, V Preliminary ASK pin enables the PA, FSK OUT and FSK pins are not ASK CRYSTAL CIRCUIT XTAL X1 rfPIC12F675K/F/H C1 (1) Transmit Frequency (MHz) XTAL ( 433.646 433.618 433.595 433.5895 433.5856 433.579 DDRF = 3V,  2003 Microchip Technology Inc. ...

  • Page 53

    ... Note 1: Standard Operating Conditions, T  2003 Microchip Technology Inc. In FSK mode the DATA enable the PA. The FSK circuit is shown in Figure 9-6. Use accurate crystals for narrow bandwidth systems and large values for C1 to reduce frequency drift. FIGURE 9-3: ...

  • Page 54

    ... DDRF rfPIC12F675K SSRF C2 1000 120 4.7 kΩ 100 BT1 + CR2032 - 3V Lithium Cell Preliminary FSK OUT 15 DATA FSK 14 DATA ASK SW2 SW1 V SSRF 11 ANT Loop Antenna FSK OUT +V 15 FSK 14 ASK SW2 SW1 V SSRF 11 ANT Loop Antenna  2003 Microchip Technology Inc. ...

  • Page 55

    ... The REFCLK output can connect directly to the T0CKI or T1CKI. The REFCLK output frequency is the crystal oscillator divided the rfPIC12F675K and rfPIC12F675F. For the rfPIC12F675H the crystal oscillator is divided by 8. Layout considerations - Keep the clock trace short and narrow yet as far as possible from other traces to reduce capacitance and the associated current draw ...

  • Page 56

    ... Low Voltage Output Disable The rfPIC12F675 transmitter has a built in low voltage disable centered at about 1.85V. If the supply voltage drops below this voltage the power amplifier is disabled to prevent uncontrolled transmissions. DS70091A-page 54 Preliminary  2003 Microchip Technology Inc. ...

  • Page 57

    ... Watchdog Timer (WDT) • SLEEP • Code protection • ID Locations • In-Circuit Serial Programming  2003 Microchip Technology Inc. rfPIC12F675 The rfPIC12F675 has a Watchdog Timer that is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up ...

  • Page 58

    ... R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 CPD CP BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0 (1) (2) (4) ( Writable bit U = Unimplemented bit, read as ‘0’ bit is set 0 = bit is cleared Preliminary memory space (2000h - R/P-1 R/P-1 R/P-1 R/P-1 bit bit is unknown  2003 Microchip Technology Inc. ...

  • Page 59

    ... C1 and C2 series resistor may be required for AT strip cut crystals varies with the Oscillator mode selected (Approx. value = 10 MΩ).  2003 Microchip Technology Inc. FIGURE 10-2: Clock from External System Open Note 1: Functions as GP4 in EC Osc mode. TABLE 10-1: ...

  • Page 60

    ... OSC /4. Calibrating the Internal Oscillator Microchip Development CALIBRATING THE INTERNAL OSCILLATOR STATUS, RP0 ;Bank 1 3FFh ;Get the cal value OSCCAL ;Calibrate STATUS, RP0 ;Bank 0 OSC /4) is output on the GP4/OSC2/ OSC /4 can be used for test purposes or  2003 Microchip Technology Inc ...

  • Page 61

    ... Ripple Counter RC OSC Note 1: This is a separate oscillator from the INTOSC/EC oscillator.  2003 Microchip Technology Inc. rfPIC12F675 They are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different RESET situations as indicated in Table 10-4 ...

  • Page 62

    ... OSC1 input) delay after the PWRT delay is over. This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP declines. Preliminary DD to  2003 Microchip Technology Inc. ...

  • Page 63

    ... Table 10-6 shows the RESET conditions for some special registers, while Table 10-7 shows the RESET conditions for all the registers.  2003 Microchip Technology Inc. On any RESET (Power-on, Brown-out, Watchdog, etc.), the chip will remain in RESET until V DD ...

  • Page 64

    ... Preliminary Wake-up from SLEEP PWRTE = 1 OSC OSC 1024•T 1024•T — — Value on all Value on Bit 0 other POR, BOD (1) RESETS 0001 1xxx 000q quuu C ---- --0x ---- --uq BOD PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --10 ---- --uu  2003 Microchip Technology Inc. ...

  • Page 65

    ... Comparator input changing, bit Timer1 rolling over, bit All other interrupts generating a wake-up will cause these bits RESET was due to brown-out, then bit All other RESETS will cause bit  2003 Microchip Technology Inc. • MCLR Reset during normal operation • MCLR Reset during SLEEP • ...

  • Page 66

    ... MCLR Internal POR PWRT Time-out OST Time-out Internal RESET FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out Internal RESET DS70091A-page 64 PWRT T OST T PWRT T T OST T PWRT T OST Preliminary  2003 Microchip Technology Inc. ): CASE CASE ...

  • Page 67

    ... Figure 10-11). The latency is the same for one or two- cycle instructions. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The  2003 Microchip Technology Inc. interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. ...

  • Page 68

    ... IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR1IF TMR1IE CMIF CMIE ADIF ADIE EEIF EEIE DS70091A-page 66 T0IF Wake-up (If in SLEEP mode) T0IE INTF INTE GPIF GPIE PEIE GIE Preliminary  2003 Microchip Technology Inc. Interrupt to CPU ...

  • Page 69

    ... Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set any time during the Q4-Q1 cycles.  2003 Microchip Technology Inc. 10.4.3 GPIO INTERRUPT An input change on GPIO change sets the GPIF (INTCON< ...

  • Page 70

    ... WDT time-out occurs. Preliminary Value on all Value on Bit 0 other POR, BOD RESETS 0000 0000 0000 000u GPIF TMR1IF 00-- 0--0 00-- 0--0 TMR1IE 00-- 0--0 00-- 0--0 SLEEP instruction). During normal SLEEP instructions clear the WDT DD = Min., Temperature = Max., Max.  2003 Microchip Technology Inc. ...

  • Page 71

    ... ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify. Only the Least Significant 7 bits of the ID locations are used.  2003 Microchip Technology Inc 8-bit Prescaler ...

  • Page 72

    ... Interrupt Latency (Note 2) Processor in SLEEP PC+2 PC Inst( Inst( Dummy cycle Preliminary instruction is being executed, the SLEEP instruction. If the GIE bit is SLEEP is not desirable, the user after the SLEEP instruction. 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h)  2003 Microchip Technology Inc. ...

  • Page 73

    ... The V DD connection on MCLR may not be required if the pin is configured as GP3. Do not place sensitive circuitry on the GP3/MCLR pin PP without protection since the V signal goes well above DD V during programming.  2003 Microchip Technology Inc. FIGURE 10-15 GP5 GP4 GP3 10 ...

  • Page 74

    ... Stack Program Memory For more information, see 8-Pin MPLAB ICD 2 Header Information Sheet (DS51292) available on Microchip’s website (www.microchip.com). Socket Socket Standoff Programmer Preliminary  2003 Microchip Technology Inc. ICDCLK, ICDDATA 1 level Address 0h must be NOP 300h - 3FEh To MPLAB ICE 2000 PCM12XB0 ...

  • Page 75

    ... A read operation is performed on a register even if the instruction writes to that register.  2003 Microchip Technology Inc. rfPIC12F675 For example, a CLRF GPIO instruction will read GPIO, clear all the data bits, then write the result back to GPIO ...

  • Page 76

    ... TO,PD 0000 0110 0100 1kkk kkkk kkkk Z 1000 kkkk kkkk 00xx kkkk kkkk 0000 0000 1001 01xx kkkk kkkk 0000 0000 1000 TO,PD 0000 0110 0011 C,DC,Z 110x kkkk kkkk Z 1010 kkkk kkkk ™ Mid-Range MCU  2003 Microchip Technology Inc. ...

  • Page 77

    ... Operation: Status Affected: Z Description: AND the W register with register 'f the result is stored in the W register the result is stored back in register 'f'.  2003 Microchip Technology Inc. rfPIC12F675 BCF Bit Clear f Syntax: [label] BCF 0 ≤ f ≤ 127 Operands: 0 ≤ b ≤ → ...

  • Page 78

    ... DECF Decrement f Syntax: [label] DECF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] ( → (destination) Operation: Status Affected: Z Description: Decrement register 'f the result is stored in the W register the result is stored back in register 'f'. Preliminary  2003 Microchip Technology Inc. f,d ...

  • Page 79

    ... Operation: Status Affected: Z Description: The contents of register 'f' are incremented the result is placed in the W register the result is placed back in register 'f'.  2003 Microchip Technology Inc. rfPIC12F675 INCFSZ Increment f, Skip if 0 Syntax: [ label ] 0 ≤ f ≤ 127 Operands: d ∈ [0,1] ( → (destination), ...

  • Page 80

    ... Return with Literal label ] RETLW k 0 ≤ k ≤ 255 k → (W); TOS → PC None The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.  2003 Microchip Technology Inc. ...

  • Page 81

    ... The contents of register 'f' are rotated one bit to the right through the Carry Flag the result is placed in the W register the result is placed back in register 'f'. C Register f  2003 Microchip Technology Inc. rfPIC12F675 SLEEP Syntax: [ label ] SLEEP Operands: None 00h → WDT, Operation: 0 → ...

  • Page 82

    ... Syntax: [label] 0 ≤ f ≤ 127 Operands: d ∈ [0,1] (W) .XOR. (f) → (destination) Operation: Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f'. Preliminary  2003 Microchip Technology Inc. XORWF f,d ...

  • Page 83

    ... L - PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog  2003 Microchip Technology Inc. rfPIC12F675 12.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows based application that contains: • ...

  • Page 84

    ... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high speed simulator is designed to debug, analyze and optimize time intensive DSP conversion, routines. Preliminary excellent, economical software  2003 Microchip Technology Inc. ...

  • Page 85

    ... The PC platform and Microsoft Windows 32-bit operating system were cho- sen to best make these features available in a simple, unified application.  2003 Microchip Technology Inc. rfPIC12F675 12.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed USB interface ...

  • Page 86

    ... The PICDEM 17 demonstration board supports program download and execution from external on-board FLASH memory. A generous prototype area is available for user hardware expansion. Preliminary PIC17C762 and PIC17C766. A  2003 Microchip Technology Inc. ...

  • Page 87

    ... Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin FLASH PIC microcontrollers, as well as many future planned devices.  2003 Microchip Technology Inc. 12.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...

  • Page 88

    ... NOTES: DS70091A-page 86 Preliminary  2003 Microchip Technology Inc. ...

  • Page 89

    ... Note: Voltage spikes below the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus, Ω a series resistor of 50-100 SS this pin directly  2003 Microchip Technology Inc. ............................................................................................... -0.3 to +7.0V SS ............................................................................ -0. SSRF .............................................-0. )...............................................................................................................± ).........................................................................................................± ∑(V ...

  • Page 90

    ... WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS70091A-page Microcontroller Frequency (MHz Microcontroller Frequency (MHz) Preliminary 20 20  2003 Microchip Technology Inc. ...

  • Page 91

    ... WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C ≤ T ≤ +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2.2 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency.  2003 Microchip Technology Inc Microcontroller Frequency (MHz) Preliminary rfPIC12F675 20 DS70091A-page 89 ...

  • Page 92

    ... Output Power = 9 dBm 1.8 1.85 1 can be lowered in SLEEP mode without losing RAM data. Preliminary ≤ +85°C for industrial A ≤ +125°C for extended A Conditions OSC < MHz: Z OSC < F < MHz OSC > 10 MHz =+23°C, RFEN = V A DDRF  2003 Microchip Technology Inc. ...

  • Page 93

    ... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. 3: Total device current is the sum of I  2003 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40°C ≤ ...

  • Page 94

    ... PD DD PDRF DDRF from V and I from V Preliminary Conditions Note REF WDT, BOD, Comparators and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV REF Current ( Current (1) A/D Current RF Transmitter with RFEN  2003 Microchip Technology Inc. ...

  • Page 95

    ... The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. 3: Total device current is the sum of I  2003 Microchip Technology Inc. -E (Extended) Standard Operating Conditions (unless otherwise stated) -40°C ≤ T ...

  • Page 96

    ... PDRF from V and I from V Preliminary ≤ +125°C for extended Conditions Note REF WDT, BOD, Comparators and T1OSC disabled (1) WDT Current (1) BOD Current (1) Comparator Current (1) CV REF Current ( Current (1) A/D Current RF Transmitter, RFEN=V SSRF current DD . DDRF .  2003 Microchip Technology Inc. ...

  • Page 97

    ... Note 1: The supply current is mainly a function of the operating voltage and frequency. Other factors such as output loading and temperature also have an impact on the current consumption. 2: Total device current is the sum of I  2003 Microchip Technology Inc. K Standard Operating Conditions (unless otherwise stated) = +23° ...

  • Page 98

    ... DD V µA ≤ V ≤ PIN DD µA ≤ V ≤ PIN DD V µA ≤ V ≤ PIN DD , XT, HS and LP osc configuration 8.5 mA 4.5V (Ind 1.6 mA 4.5V (Ind 1.2 mA 4.5V (Ext -3.0 mA 4.5V (Ind -1.3 mA 4.5V (Ind -1.0 mA 4.5V (Ext.)  2003 Microchip Technology Inc. ...

  • Page 99

    ... Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: See Section 8.5.1 for additional information. 2: These limits are tested at room temperature.  2003 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T -40°C ≤ T Min Typ† ...

  • Page 100

    ... Invalid (Hi-impedance) L Low FIGURE 13-4: LOAD CONDITIONS Load Condition 1 Pin 464Ω for all pins 15 pF for OSC2 output DS70091A-page 98 T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance Load Condition Pin SS V Preliminary  2003 Microchip Technology Inc. ...

  • Page 101

    ... All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices.  2003 Microchip Technology Inc ...

  • Page 102

    ... DD 0°C ≤ T ≤ +85°C A ≤ 5.5V DD -40°C ≤ T ≤ +85°C (IND) A -40°C ≤ T ≤ +125°C (EXT) A µ 2.0V, -40°C to +85°C µ 3.0V, -40°C to +85°C µ 5.0V, -40°C to +85°C  2003 Microchip Technology Inc. ...

  • Page 103

    ... INT pin high or low time 23 Trbp GPIO change INT high or low time * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4xT  2003 Microchip Technology Inc ...

  • Page 104

    ... I/O Pins FIGURE 13-8: BROWN-OUT DETECT TIMING AND CHARACTERISTICS DD V VDD B (Device in Brown-out Detect) RESET (due to BOD) Note delay only if PWRTE bit in configuration word is programmed to ‘0’. DS70091A-page 102 (Device not in Brown-out Detect time-out Preliminary  2003 Microchip Technology Inc. 34 (1) ...

  • Page 105

    ... Brown-out Detect Pulse Width * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2003 Microchip Technology Inc. rfPIC12F675 Min Typ† ...

  • Page 106

    ... N 0 — 15 — 30 — 0 — 15 — 30 — Greater of: — — DC — OSC * — Preliminary  2003 Microchip Technology Inc. 48 Conditions — ns — ns — ns — ns — prescale value (2, 4, ..., 256) — ns — ns — ns — ns — ns — ns — prescale value ( — ns 200* ...

  • Page 107

    ... Unit Resistor Value (R) (1) Settling Time * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.  2003 Microchip Technology Inc. Standard Operating Conditions -40°C to +125°C (unless otherwise stated) Min Typ ...

  • Page 108

    ... Preliminary Conditions REF = 5.0V REF = 5.0V REF V = 5.0V REF = 5.0V REF = 5.0V ≤ V ≤ AIN REF V + Absolute minimum to ensure 10-bit accuracy AIN During V acquisition. HOLD AIN Based on differential During A/D conversion cycle.  2003 Microchip Technology Inc. ...

  • Page 109

    ... Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: ADRES register may be read on the following T 2: See Section 7.1 for minimum conditions.  2003 Microchip Technology Inc. (1) /2) 131 ...

  • Page 110

    ... LSb (i.e., 4 4.096V) from the last sampled voltage (as stored on C HOLD ). If the A/D clock source is selected CY as RC, a time added before the A/D clock starts. This allows the SLEEP instruction to be executed.  2003 Microchip Technology Inc. ...

  • Page 111

    ... RF Output Power in Step Output Power in Step Output Power in Step Phase Noise SPUR P Spurious Emissions  2003 Microchip Technology Inc. Standard Operating Conditions +23°C (unless otherwise stated) DDRF V = 3.0V (unless otherwise stated 315 MHz (unless otherwise stated) Min Typ Max Units 290 — ...

  • Page 112

    ... TABLE 13-12: rfPIC12F675F RF TRANSMITTER SPECIFICATIONS (434 MHz) RF Transmitter Specifications Sym Characteristics C F VCO Frequency XTAL F Crystal Frequency F REF Reference Frequency L C Load Capacitance O C Static Capacitance S R Series Resistance SPUR A Spurious response ∆F VDD Frequency Stability vs V DDRF ∆F TA Frequency Stability vs Temp ∆ ...

  • Page 113

    ... RF Output Power in Step Output Power in Step Output Power in Step Phase Noise SPUR P Spurious Emissions  2003 Microchip Technology Inc. Standard Operating Conditions +23°C (unless otherwise stated) DDRF V = 3.0V (unless otherwise stated 868.3 MHz (unless otherwise stated) Min Typ Max Units 850 — ...

  • Page 114

    ... NOTES: DS70091A-page 112 Preliminary  2003 Microchip Technology Inc. ...

  • Page 115

    ... FIGURE 14-2: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2.0 2.5  2003 Microchip Technology Inc. vs. V OVER TEMP (-40°C TO +25°C) DD Typical Baseline 3.5 4 4.5 V (V) DD vs. V OVER TEMP (+85°C) DD Typical Baseline ...

  • Page 116

    ... DS70091A-page 114 vs. V OVER TEMP (+125°C) DD Typical Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (-40°C TO +25°C) DD Maximum Baseline 3.5 4 4.5 V (V) DD Preliminary 125 5.0 5.5 - 5.5  2003 Microchip Technology Inc. ...

  • Page 117

    ... FIGURE 14-6: MAXIMUM I PD 9.0E-06 8.0E-06 7.0E-06 6.0E-06 5.0E-06 4.0E-06 3.0E-06 2.0E-06 1.0E-06 0.0E+00 2.0 2.5  2003 Microchip Technology Inc. vs. V OVER TEMP (+85°C) DD Maximum Baseline I PD 3.0 3.5 4.0 4.5 V (V) DD vs. V OVER TEMP (+125°C) DD Maximum Baseline ...

  • Page 118

    ... WITH BOD ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical BOD 4.5 V (V) DD WITH CMP ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical Comparator I PD 3.0 3.5 4.0 4.5 V (V) DD Preliminary - 125 5 5.5 - 125 5.0 5.5  2003 Microchip Technology Inc. ...

  • Page 119

    ... FIGURE 14-10: TYPICAL I PD 3.5E-07 3.0E-07 2.5E-07 2.0E-07 1.5E-07 1.0E-07 5.0E-08 0.0E+00 2 2.5  2003 Microchip Technology Inc. WITH A/D ENABLED vs. V OVER TEMP (-40°C TO +25°C) DD Typical A 3.5 4 4.5 V (V) DD WITH A/D ENABLED vs. V OVER TEMP (+85°C) DD Typical A/D I ...

  • Page 120

    ... DS70091A-page 118 WITH A/D ENABLED vs. V OVER TEMP (+125°C) DD Typical A 3.5 4 4.5 ( WITH T1 OSC ENABLED vs Typical 3.0 3.5 4.0 4.5 ( Preliminary 125 5 5.5 OVER TEMP (-40°C TO +125°C), - 125 5.0 5.5  2003 Microchip Technology Inc. ...

  • Page 121

    ... FIGURE 14-14: TYPICAL 2.5  2003 Microchip Technology Inc. WITH CV ENABLED vs. V OVER TEMP (-40°C TO +125°C) REF DD Typical CV I REF PD 3 3.5 4 4.5 V (V) DD WITH WDT ENABLED vs. V OVER TEMP (-40°C TO +125°C) DD Typical WDT ...

  • Page 122

    ... DS70091A-page 120 = 3.5V) DD Internal Oscillator Frequency vs Temperature 0°C 25°C 85°C Temperature (°C) Internal Oscillator Frequency 3.0V 3.5V 4.0V 4.5V V (V) DD Preliminary -3sigma average +3sigma 125°C WITH 0.1µF AND 0.01µF DD -3sigma average +3sigma 5.0V 5.5V  2003 Microchip Technology Inc. ...

  • Page 123

    ... FIGURE 14-17: TYPICAL WDT PERIOD vs 2.5  2003 Microchip Technology Inc. (-40°C TO +125°C) DD WDT Time-out 3 3.5 4 4.5 V (V) DD Preliminary rfPIC12F675 - 125 5 5.5 DS70091A-page 121 ...

  • Page 124

    ... NOTES: DS70091A-page 122 Preliminary  2003 Microchip Technology Inc. ...

  • Page 125

    ... Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2003 Microchip Technology Inc. rfPIC12F675 Example rfPIC™ ...

  • Page 126

    ... Preliminary α A2 MILLIMETERS MIN NOM MAX 20 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.18 5.11 5.25 5.38 7.06 7.20 7.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0.  2003 Microchip Technology Inc. ...

  • Page 127

    ... APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet.  2003 Microchip Technology Inc. rfPIC12F675 Preliminary DS70091A-page 125 ...

  • Page 128

    ... NOTES: DS70091A-page 126 Preliminary  2003 Microchip Technology Inc. ...

  • Page 129

    ... Write Verify ................................................................. 47 Code Protection .................................................................. 69 Comparator ......................................................................... 33 Associated Registers .................................................. 38 Configuration............................................................... 35 Effects of a RESET ..................................................... 37 I/O Operating Modes................................................... 35 Interrupts..................................................................... 38  2003 Microchip Technology Inc. Operation.................................................................... 34 Operation During SLEEP............................................ 37 Output......................................................................... 36 Reference ................................................................... 37 Response Time .......................................................... 37 Comparator Specifications................ 105, 108, 109, 110, 111 Comparator Voltage Reference Specifications................. 105 Configuration Bits ............................................................... 56 Configuring the Voltage Reference ...

  • Page 130

    ... Special Function Registers ................................................... 6 Special Functions Registers Summary................................. 7 T Time-out Sequence ............................................................ 61 Timer0................................................................................. 25 Associated Registers .................................................. 27 External Clock............................................................. 26 Interrupt ...................................................................... 25 Operation .................................................................... 25 T0CKI ......................................................................... 26 Timer1 Associated Registers .................................................. 31 Asynchronous Counter Mode ..................................... 31 Reading and Writing ........................................... 31 Interrupt ...................................................................... 29 Modes of Operations .................................................. 29 Operation During SLEEP............................................ 31 Oscillator..................................................................... 31 Prescaler .................................................................... 29 Preliminary  2003 Microchip Technology Inc. ...

  • Page 131

    ... Timer0 and Timer1 External Clock ........................... 104 Timer1 Incrementing Edge.......................................... 29 Timing Parameter Symbology............................................. 98 U UHF ASK/FSK Transmitter CEPT .......................................................................... 49 FCC............................................................................. 49 Radio Frequency......................................................... 49 Transmitter.................................................................. 49 V Voltage Reference Accuracy/Error ..................................... 37 W Watchdog Timer Summary of Registers ................................................ 69 Watchdog Timer (WDT) ...................................................... 68 WWW, On-Line Support ....................................................... 2  2003 Microchip Technology Inc. Preliminary DS70091A-page 129 ...

  • Page 132

    ... NOTES: DS70091A-page 130 Preliminary  2003 Microchip Technology Inc. ...

  • Page 133

    ... Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events  2003 Microchip Technology Inc. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...

  • Page 134

    ... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70091A-page 132 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS70091A Preliminary  2003 Microchip Technology Inc. ...

  • Page 135

    ... Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. XXX Examples: Pattern a) rfPIC12F675F – E/SS 301 = Extended Temp., SSOP package, 434 MHz, QTP pattern #301 b) rfPIC12F675HT – I/SS = Industrial Temp., SSOP package, 868 MHz, Tape and Reel Preliminary ...

  • Page 136

    ... Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No ...