RFPIC12F675F-I/SS Microchip Technology, RFPIC12F675F-I/SS Datasheet - Page 20

IC MCU 1KX14 RF FSK/ASK 20SSOP

RFPIC12F675F-I/SS

Manufacturer Part Number
RFPIC12F675F-I/SS
Description
IC MCU 1KX14 RF FSK/ASK 20SSOP
Manufacturer
Microchip Technology
Series
PIC®r
Datasheets

Specifications of RFPIC12F675F-I/SS

Package / Case
20-SSOP
Frequency
380MHz ~ 450MHz
Applications
RKE, Security Systems
Modulation Or Protocol
ASK, FSK
Data Rate - Maximum
40 kbps
Power - Output
10dBm
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
Voltage - Supply
2V ~ 5.5V
Operating Temperature
-40°C ~ 125°C
Processor Series
RFPIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000, DV164102, AC164101, AC164103
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
1.75 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164103 - MODULE RCVR RFPIC 433MHZAC164101 - MODULE TRANSMITTER RFPIC 433MHZDV164102 - KIT DEV RFPICKIT KIT 1AC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3188156

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rfPIC12F675
REGISTER 3-2:
REGISTER 3-3:
DS70091A-page 18
bit 7-6:
bit 5-0:
bit 7-6
bit 5-4
bit 3
bit 2-0
TRISIO — GPIO TRISTATE REGISTER (ADDRESS: 85h)
WPU — WEAK PULL-UP REGISTER (ADDRESS: 95h)
bit 7
Unimplemented: Read as ’0’
TRISIO<5:0>: General Purpose I/O Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output.
Unimplemented: Read as ‘0’
WPU<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
WPU<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.
bit 7
Legend:
R = Readable bit
- n = Value at POR
Legend:
R = Readable bit
- n = Value at POR
Note:
U-0
U-0
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISIO = 0).
TRISIO<3> always reads 1.
U-0
U-0
TRISIO5
R/W-x
WPU5
R/W-1
Preliminary
W = Writable bit
’1’ = Bit is set
W = Writable bit
’1’ = Bit is set
TRISIO4
R/W-x
WPU4
R/W-1
TRISIO3
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
R-1
R/W-1
WPU2
TRISIO2 TRISIO1
R/W-x
 2003 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-1
WPU1
R/W-x
TRISIO0
WPU0
R/W-1
R/W-x
bit 0
bit 0

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