RFPIC12F675F-I/SS Microchip Technology, RFPIC12F675F-I/SS Datasheet - Page 48

IC MCU 1KX14 RF FSK/ASK 20SSOP

RFPIC12F675F-I/SS

Manufacturer Part Number
RFPIC12F675F-I/SS
Description
IC MCU 1KX14 RF FSK/ASK 20SSOP
Manufacturer
Microchip Technology
Series
PIC®r
Datasheets

Specifications of RFPIC12F675F-I/SS

Package / Case
20-SSOP
Frequency
380MHz ~ 450MHz
Applications
RKE, Security Systems
Modulation Or Protocol
ASK, FSK
Data Rate - Maximum
40 kbps
Power - Output
10dBm
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
Voltage - Supply
2V ~ 5.5V
Operating Temperature
-40°C ~ 125°C
Processor Series
RFPIC12F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ICE2000, DV164102, AC164101, AC164103
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
1.75 KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164103 - MODULE RCVR RFPIC 433MHZAC164101 - MODULE TRANSMITTER RFPIC 433MHZDV164102 - KIT DEV RFPICKIT KIT 1AC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3188156

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rfPIC12F675
8.1
The EEADR register can address up to a maximum of
128 bytes of data EEPROM. Only seven of the eight
bits in the register (EEADR<6:0>) are required. The
MSb (bit 7) is ignored.
The upper bit should always be ‘0’ to remain upward
compatible with devices that have more data EEPROM
memory.
8.2
EECON1 is the control register with four low order bits
physically implemented. The upper four bits are non-
implemented and read as '0's.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
REGISTER 8-3:
DS70091A-page 46
EEADR
EECON1 AND EECON2
REGISTERS
bit 7-4
bit 3
bit 2
bit 1
bit 0
EECON1 — EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
bit 7
Unimplemented: Read as ‘0’
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR: Write Control bit
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit
0 = Write cycle to the data EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
0 = Does not initiate an EEPROM read
Legend:
S = Bit can only be set
R = Readable bit
- n = Value at POR
U-0
normal operation or BOD detect)
can only be set, not cleared, in software.)
can only be set, not cleared, in software.)
U-0
U-0
Preliminary
W = Writable bit
’1’ = Bit is set
U-0
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal opera-
tion. In these situations, following RESET, the user can
check the WRERR bit, clear it, and rewrite the location.
The data and address will be cleared, therefore, the
EEDATA and EEADR registers will need to be re-
initialized.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
WRERR
R/W-x
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
WREN
R/W-0
 2003 Microchip Technology Inc.
x = Bit is unknown
R/S-0
WR
R/S-0
RD
bit 0

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