RFPIC12F675F-I/SS Microchip Technology, RFPIC12F675F-I/SS Datasheet - Page 69

• Manufacturer Part Number: RFPIC12F675F-I/SS
• Description: IC MCU 1KX14 RF FSK/ASK 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC®r

Specifications of RFPIC12F675F-I/SS

• Package / Case: 20-SSOP
• Frequency: 380MHz ~ 450MHz
• Applications: RKE, Security Systems
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 40 kbps
• Power - Output: 10dBm
• Current - Transmitting: 14mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
• Voltage - Supply: 2V ~ 5.5V
• Operating Temperature: -40°C ~ 125°C
• Processor Series: RFPIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ICE2000, DV164102, AC164101, AC164103
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 1.75 KB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164103 - MODULE RCVR RFPIC 433MHZAC164101 - MODULE TRANSMITTER RFPIC 433MHZDV164102 - KIT DEV RFPICKIT KIT 1AC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3188156

10.4.1
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, of
falling, if INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The GP2/INT
interrupt can wake-up the processor from SLEEP if the
INTE bit was set prior to going into SLEEP. The status
of the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 10.9 for details on SLEEP and Figure 10-13 for
timing of wake-up from SLEEP through GP2/INT
interrupt.
10.4.2
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 4.0.
FIGURE 10-11:
 2003 Microchip Technology Inc.
INSTRUCTION FLOW
Note:
Note 1: INTF flag is sampled here (every Q1).
GIE bit
(INTCON<7>)
INTF Flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
Executed
Instruction
Fetched
PC
enabled/disabled
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
on
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
GP2/INT INTERRUPT
TMR0 INTERRUPT
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3
the
Q1
Inst (PC-1)
GP2/INT
Inst (PC)
INT PIN INTERRUPT TIMING
1
Q2
PC
by
Q3
4
setting/clearing
pin,
Q4
5
Q1
the
Inst (PC+1)
Inst (PC)
Q2
1
INTF
PC+1
CY
Q3
. Synchronous latency = 3 T
T0IE
Preliminary
bit
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
10.4.3
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus individual pins can be configured through the
IOC register.
10.4.4
See Section 6.9 for description of comparator interrupt.
10.4.5
After a conversion is complete, the ADIF flag (PIR<6>)
is set. The interrupt can be enabled/disabled by setting
or clearing ADIE (PIE<6>).
See Section 7.0 for operation of the A/D converter
interrupt.
PC+1
—
Note:
Q3
Q4
CY
2
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF inter-
rupt flag may not get set.
, where T
GPIO INTERRUPT
COMPARATOR INTERRUPT
A/D CONVERTER INTERRUPT
Q1
Dummy Cycle
Inst (0004h)
Q2
CY
0004h
rfPIC12F675
= instruction cycle time. Latency
Q3
Q4
Q1
DS70091A-page 67
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4