OL2300NHN/F,118 NXP Semiconductors, OL2300NHN/F,118 Datasheet

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OL2300 Fractional-N PLL based transmitter Rev. 2 — 28 October 2010 1. General description The OL2300 is a UHF ASK/FSK fractional-N transmitter with a fully integrated fractional-N Phase-Locked Loop (PLL) frequency synthesizer and a power amplifier to drive an external ...

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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −25 °C to +85 °C OL2300NHN [1] When the exposed die attach pad is used, it must be connected to GND. 4. Functional diagram OL2300 TEST2 TEST LOGIC TEST1/SDO EN SCK SPI SDIO CKOUT V POWER SUPPLY ...

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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Symbol SCK EN XTAL2 XTAL1 V DD VREG V DDA V SSA V SS(PA) PAOUT DDD(PA) TEST2 TEST1/SDO CKOUT SDIO OL2300 Product data sheet terminal 1 index area SCK XTAL2 4 XTAL1 Transparent top view Pin configuration SOT758-1 (HVQFN16) ...

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... NXP Semiconductors 6. Functional description 6.1 Functional blocks overview 6.1.1 Power management, voltage regulator The supply voltage source is connected between pin SS(PA) An integrated low-dropout voltage regulator is used to supply the PLL and the PA-driver with a reduced, regulated voltage. This helps keep the current consumption and the supply voltage dependencies of the PLL as low as possible ...

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... NXP Semiconductors 6.1.2 Interface and control logic 6.1.2.1 Configurable 3-wire or 4-wire interface The OL2300 can be configured via a simple Serial Peripheral Interface (SPI). The interface itself can be configured for 3-wire or 4-wire mode. The 4-wire mode uses pin TEST1 as Serial Data Output SDO when the SDIO is used as input (see EN pin must be set to enable communication via the 3 or 4-wire serial interface ...

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... NXP Semiconductors SDIO is the configurable bidirectional data input/output pin of the serial interface. By default, the bidirectional mode is configured, so SDIO is used for both input and output data transmission. If ENSDO in register ACON2 is set, SDIO is used as input only and TEST1 is configured as data output SDO (4-wire interface). The SDO pin is high ohmic until data is written ...

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... NXP Semiconductors The power amplifier output (pin PAOUT) requires an external DC path to pin V established by the antenna loop or a dedicated bias coil. A dedicated ground pin (V is provided to improve the RF properties of the circuitry and must be connected to pin V Best efficiency is achieved when the output voltage swing at pin PAOUT yields one volt ...

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... NXP Semiconductors exited when either EN is set LOW directly, or when EN is set LOW in a synchronized way with the edge of the last data-bit (in both cases the PLL Active mode is entered) or upon direct SPI register setting (then XTAL active mode is entered POR or power fail condition occurs during a transmit sequence, the XTAL active mode is entered ...

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... NXP Semiconductors Powerdown >2 XTAL t w(clk) PLL-Active >2 XTAL t w(clk) Fig 6. State diagram 6.3 Reference clock generation The crystal frequency is used as a reference for both the fractional-N PLL and the baud rate generation. The oscillator is designed to work in parallel resonance mode of the crystal. In addition two external load capacitances are required to operate the crystal at the specified nominal frequency ...

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... NXP Semiconductors C = load Table 5. Variable C load1 C load2 C XTAL1 C XTAL2 C PCB(par) Fig 7. The oscillator is constructed using an inverting gain stage between the two XTAL pins with a clock buffer stage in series. The feedback resistor between XTAL1 and XTAL2 is used to define the DC operating point to keep the amplifier working in linear region. ...

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... NXP Semiconductors Fig 8. To additionally reduce the total current consumption the power supply of the crystal oscillator can be switched from V control bit ENXR in the special function register TXCON. Table 6. ENXR ENXR is set, the oscillator supply is automatically changed to a regulated supply when the transmit-state is entered. The XTAL supply is switched back to the unregulated supply when the transmit-state is exited ...

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... NXP Semiconductors Fig 9. 6.4.1 Power amplifier modes The bits PAM0 and PAM1 located in the special function register TXCON can be used to choose between three regulated and one unregulated power modes. The regulated modes should be used for applications where the output power should be independent from changes of the supply voltage and ambient temperature ...

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... NXP Semiconductors The available output power is a function of the actual VCO frequency, so the higher the VCO frequency and its supply voltage (V low VCO frequency selection is desirable for Japan due to the present limitations regarding radiated output power. 6.4.2 ACON power amplifier amplitude control The control registers ACON0, ACON1 and ACON2, control the power amplifier driver stage in all four power modes for either amplitude fine-tuning or ASK modulation means ...

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... NXP Semiconductors Fig 11. ASK modulation timing If TXDATA is high then AMOUT is set and the amplitude is given by the content AML[3:0] in register ACON2 and the settings of ASK0 and ASK1. If ‘D’ is cleared ASK0 located in register ACON0 determines between ASK and FSK operation. Alternatively if “D” is set, ASK1 is used ...

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... NXP Semiconductors Table 14. Bit 7 X R/W [1] MRCON is also used for soft-FSK. The configured ramp time also defines the maximum possible data rate for ASK operation. The ramp time can be calculated by SASK For RMP0 to RMP6 is not equal to 0, the maximum baud rate is given by: ...

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... NXP Semiconductors 6.4.8 ENPF, enable power fail detection If set, the built in power fail detection (brown out detection) is enabled. In this case the PLL and the PA are switched off if the supply voltage at V guarantee proper operation of the line regulator. This also includes the proper function of the PLL circuit ...

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... NXP Semiconductors 6.5 Frequency control and FSK operation FSK modulation is applied if the ASK control bit of the selected ACON register is cleared. ACON0 or ACON1 can then be selected for the FSK transmission amplitude setting dependent on the setting of the transmit-command control-bit ‘D’, (see 6.6 Frequency control registers The operation frequency is set by the content of the frequency control registers FC1 to FC4, which each have a width of 18 bits ...

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... NXP Semiconductors 6.6.2 PLL frequency deviation (FSK) The FSK frequency deviation is set as part of the FCON (FSK modulation control) register and has a width of 8 bits. Table 21. Bit 7 FSK7 R/W FSK deviation is calculated by: Table 22. Variable f DEV FSK DEF f ref [1] f can be set to f ref ...

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... NXP Semiconductors Table 24. Bit 7 PD [1] All bits R/W. Setting the bit XOSL enables the XTAL clock divider that lowers the reference clock frequency of the PLL by a factor of 2. This allows for example the use MHz crystal for the 315 MHz ISM band. ...

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... NXP Semiconductors 6.7 Baud rate generation PD (TXCON RESET EN PAON Clk PSC f PRESCALER REF 3 PSC CSS2 PDCK PAON (TXCON) LOW CKOUT 1 11 s[1:0] 2 CSS1, CSS0 clock source select SDIO enter TX-state (command) to SFR interface Fig 14. Serial configuration interface block diagram of baud rate and data generation 6 ...

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... NXP Semiconductors The baud rate division ratio is: Remark: For synchronization reasons both baud rate counter and afterscaler are kept in reset state while the power amplifier is turned off. The prescaler will be clocked continuously whenever the XTAL oscillator is running. Table 28. BD7 6.7.2 Clock generation/selection ...

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... NXP Semiconductors Table 31. CSS2 [1] If the bit PDCK in register TXCON is set, CKOUT is set 3-state (independent from the CSS[2:0] settings). 6.7.3 Prescaler The Prescaler clock is the reference clock divided 128. The division ratio is set in the PSC[2:0] bits (See Table 32. PSC2 [1] Reset/Power-on state: if SDIO is low at the rising edge division ratio of 16 will be applied, otherwise the division ratio will remain unchanged ...

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... NXP Semiconductors 6.7.6 Synchronous mode When operating the device in synchronous mode data is clocked on the rising edge of CKOUT possible to invert this clock signal as described in signal has the effect of clocking the data presented at SDIO on the falling edge of CKOUT. The clock for the data generator has a dedicated afterscaler, therefore the CKOUT signal can run at a higher frequency if desired, as described in 6 ...

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SFR summary [1] Table 34. Special function register summary Name Description Address Bit 7 FC1H frequency configuration 1 00h high byte FC1L frequency configuration 1 01h low byte FC2H frequency configuration 2 02h high byte FC2L frequency configuration 2 ...

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... NXP Semiconductors 6.7.9 General SFR access information If SCK is high at the rising edge of EN the data is transferred with the rising edge of SCK and if SCK is low at the rising edge of EN, the data is transferred with the falling edge of SCK (as shown in the write and read-access diagrams). Please note these statements are true at every rising edge of EN ...

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... NXP Semiconductors 6.7.9.3 Read access to SFR EN SCK DI DO DIO Fig 17. Read serial interface timing diagram 6.7.9.4 Access to SFR with auto-increment function If the SPI clock SCK is still applied after the first transferred 8 data bits, the auto-increment function automatically increases the address for the following next 8 data bits by one. This enables writing data to a contiguous range of bytes without the need to set the address for every single data-byte ...

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Write access to SFR with auto-increment function EN SCK SDIO ...

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... NXP Semiconductors 6.7.10 Transmit data command 6.7.10.1 Transmit configuration Some transmit-configuration bits must be sent via SPI before every transmit command see Other configuration settings are stored in the registers and the state machine retains them until these bits are altered. 6.7.11 Description of the configuration bits 6 ...

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... NXP Semiconductors Table 35. Bit 6.7.11.6 Transmission command EN SCLK DI DO DIO Fig 20. Transmit data timing diagram contain configuration information for the transmit-operation. 6.7.11.7 Transparent data transmission (example) Bit Bit after the power amplifier is turned on. During transmission EN must be kept 1 and the data at SDIO is transmitted transparently. ...

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... NXP Semiconductors TXDATA EN SCLK DI DO SDIO Fig 21. Transmit data example 1 OL2300 Product data sheet power amplifier is switched All information provided in this document is subject to legal disclaimers. Rev. 2 — 28 October 2010 OL2300 Fractional-N PLL based transmitter ''0'' ''1'' power amplifier is switched off © NXP B.V. 2010. All rights reserved. ...

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... NXP Semiconductors 6.7.11.8 Synchronized data transmission (example): Phase 1: Bit clock output, see Bit edge of EN the actual data bit at SDIO is latched and a constant carrier will be transmitted with Manchester coding (bit until the power amplifier is turned off. Bit will be ignored and the data transmission will be done synchronized to the baud rate clock ...

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TXDATA power amplifier is switched on CLK ASC EN SCK SDIO PHASE 1; DATA TRANSMISSION EN SCK power amplifier is switched on SDIO Fig 22. Transmit data example 2 data is Manchester ...

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... NXP Semiconductors 7. Limiting values Table 36. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter ESD P T amb T stg [1] According to JEDEC, JESD 78. [2] According to JEDEC, JESD 22-A114. [3] According to JEDEC, JESD 22-A115. 8. Characteristics Table 37. Characteristics − ° ° + 2 amb DD specified). ...

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... NXP Semiconductors Table 37. Characteristics …continued − ° ° + 2 amb DD specified). Symbol Parameter Voltage regulator t start delay time d(start) C capacitance on pin VREG VREG [1] The available supply voltage range can be extended using the undervoltage detection circuitry in adaptive mode. If enabled, the minimum PLL supply voltage corresponds with the actual undervoltage detection voltage ( ...

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... NXP Semiconductors 8.1 Serial interface characteristics Table 39. I/O pins (SCK, EN, SDIO, SDO, CKOUT) − ° ° + 2 amb DD specified). Symbol Parameter V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level input current IL I HIGH-level input current IH V LOW-level output voltage OL V HIGH-level output voltage ...

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... NXP Semiconductors Table 41. Transmitter AC/DC conditions − ° ° + 2 amb DD specified). Symbol Parameter C input capacitance i t settling time s PLL synthesizer B PLL loop bandwidth PLL(loop) ϕ phase noise n ϕ phase noise n α spurious response resp(sp) t acquisition time acq [5] Power amplifier P maximum output power PAM = 3; AMH = ‘1111’; CASC = 0; ...

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... NXP Semiconductors Table 41. Transmitter AC/DC conditions − ° ° + 2 amb DD specified). Symbol Parameter [7] Modulation f modulation frequency mod [1] Maximum resistance that can be put in series with the crystal without causing oscillation dropouts [2] The given R (Oscillation margin) is tested and guaranteed only at room temperature (T s temperature and a minimum supply voltage of V [3] To guarantee sufficient oscillation start-up margin every reference application board must be individually checked by the customer ...

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... NXP Semiconductors Table 42. Component 9.1 Test setup Fig 24. Current and RF measurement set-up Fig 25. Regulator and PFD measurement set-up OL2300 Product data sheet Load tank circuit configuration for ~200 Ω 315 MHz 6 100 pF I DD,XO I DD,TX I DD,XO I DD,XOstup I DD,PLL V VREG DUT SSA ...

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... NXP Semiconductors 10. Package outline HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

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... NXP Semiconductors 11. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 11.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

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... NXP Semiconductors 11.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

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... NXP Semiconductors Fig 27. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. OL2300 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...

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... NXP Semiconductors 12. Abbreviations Table 45. Acronym ASK FSK ISM OOK PLL SPI SRD VCO CMOS IF NMOS NRZ PCB SRD 13. Revision history Table 46. Revision history Document ID Release date OL2300 v.2 20101028 • Modifications: Section • Figure • Table • T OL2300 v.1 20091116 OL2300 ...

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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

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... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...

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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Functional blocks overview 6.1.1 Power management, voltage regulator 6.1.2 Interface and control logic . . . . . . . . . . . . . . . . 5 6.1.2.1 Configurable 3-wire or 4-wire interface ...