MFRC52301HN1,151 NXP Semiconductors, MFRC52301HN1,151 Datasheet
MFRC52301HN1,151
Specifications of MFRC52301HN1,151
935282956151
MFRC52301HN1
Related parts for MFRC52301HN1,151
MFRC52301HN1,151 Summary of contents
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... ISO/IEC 14443-4 and/or ISO/IEC 14443 B anticollision are correctly implemented Using this NXP Semiconductors’ device according to ISO/IEC 14443 B may infringe third party patent rights. The MFRC523 supports contactless communication using MIFARE higher baud rates (see Section 8.3.4.11 on page The following host interfaces are provided: • ...
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... NXP Semiconductors 3. Features and benefits Highly integrated analog circuitry to demodulate and decode responses Buffered output drivers for connecting an antenna with the minimum number of external components Supports ISO/IEC 14443 A/MIFARE Supports ISO/IEC 14443 B Read/Write modes Typical operating distance in Read/Write mode depending on the ...
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... NXP Semiconductors Table 1. Quick reference data Symbol Parameter I analog supply current DDA I PVDD supply current DD(PVDD) I TVDD supply current DD(TVDD) T ambient temperature amb [1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [ and V must always be the same voltage. ...
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... NXP Semiconductors 6. Block diagram The analog interface manages the modulation and demodulation of the analog signals. The contactless UART manages the protocol requirements for the communication protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data transfers to/from the host and the contactless UART. ...
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... NXP Semiconductors SDA/NSS/RX EA I2C D1/ADR_5 SPI, UART, I FIFO CONTROL 64-BYTE FIFO BUFFER CONTROL REGISTER BANK MIFARE CLASSIC UNIT RANDOM NUMBER GENERATOR AMPLITUDE RATING REFERENCE VOLTAGE ANALOG TEST I-CHANNEL MULTIPLEXOR AMPLIFIER AND DIGITAL TO I-CHANNEL ANALOG DEMODULATOR CONVERTER VMID AUX1 AUX2 Fig 2. Detailed block diagram of the MFRC523 ...
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... NXP Semiconductors 7. Pinning information Fig 3. 7.1 Pin description Table 3. Pin description [1] Pin Symbol Type [2] 1 I2C I 2 PVDD P 3 DVDD P [3] 4 DVSS G 5 PVSS G 6 NRSTPD I 7 MFIN I 8 MFOUT O 9 SVDD P 10 TVSS G 11 TX1 O 12 TVDD P 13 TX2 O 14 ...
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... NXP Semiconductors Table 3. Pin description …continued [1] Pin Symbol Type 16 VMID AVSS G 19 AUX1 O 20 AUX2 O 21 OSCIN I 22 OSCOUT O 23 IRQ O [2] 24 SDA I/O [2] NSS I/O [2] ADR_5 I I/O [2] ADR_4 I/O [2] ADR_3 I/O [2] ADR_2 I/O [2] ADR_1 I [2] SCK I [2] DTRQ I/O [2] ADR_0 ...
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... NXP Semiconductors 8. Functional description The MFRC523 transmission module supports ISO/IEC 14443 A and ISO/IEC 14443 B Read/Write mode at various transfer speeds and modulation protocols. Fig 4. 8.1 ISO/IEC 14443 A functionality The physical level communication is shown in (1) Reader to card (MFRC523 sends data to a card). (2) Card to reader (card sends data to the MFRC523). ...
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... ISO 14443 A and ISO 14443 B. Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4). Remark: NXP Semiconductors does not offer a software library to enable design-in of the ISO 14443 B protocol. 8.3 Digital interfaces 8 ...
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... NXP Semiconductors Table 5. Pin SDA I2C 8.3.2 Serial Peripheral Interface The 5-wire Serial Peripheral Interface (SPI) is supported and enables high-speed communication with the host. The interface can manage data speeds Mbit/s. When communicating with a host, the MFRC523 acts as a slave. As such, it receives data from the external host for register settings, sends and receives data relevant for RF interface communication ...
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... NXP Semiconductors The first byte sent defines both the mode and the address. Table 6. Line MOSI MISO [ not care. Remark: The MSB must be sent first. 8.3.2.2 SPI write data To write data to the MFRC523 using SPI requires the byte order shown in possible to write up to n-data bytes by only sending one address byte. ...
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... NXP Semiconductors The write address byte must meet the following criteria: • the MSB of the first byte sets the mode. To write data to the MFRC523, the MSB is set to logic 0; see • bits [6:1] define the address • the LSB should be set to logic 0 Table 9 ...
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... NXP Semiconductors Table 11. Transfer speed (kBd) 7.2 9.6 14.4 19.2 38.4 57.6 115.2 128 230.4 460.8 921.6 1228.8 [1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds. The selectable transfer speeds shown in following equations: If BR_T0[2: transfer speed If BR_T0[2:0] > ...
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... NXP Semiconductors Table 13. Pin DTRQ (1) Reserved. Fig 9. UART read data timing diagram To write data to the MFRC523 using the UART interface, the structure shown in must be used. The first byte sent defines both the mode and the address. Table 14. Pin RX TX MFRC523_34 Product data sheet ...
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ADDRESS ( DTRQ (1) Reserved. Remark: The data byte can be sent directly after the address byte on pin RX. Fig 10. UART write data timing diagram R/W SO ADDRESS ...
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... An I C-bus interface is supported and enables implementation of a low-cost, low pin count serial bus interface to the host. The I NXP Semiconductors’ I interface can only act in slave mode. Therefore the MFRC523 does not perform clock generation or access arbitration. Fig 11. I The MFRC523 can act as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode ...
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... NXP Semiconductors 8.3.4.1 Data validity Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW. Fig 12. Bit transfer on the I 8.3.4.2 START and STOP conditions To manage the data transfer on the I are defined ...
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... NXP Semiconductors 8.3.4.4 Acknowledge An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse ...
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... EA. If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by NXP Semiconductors and set to 0101b for all MFRC523 devices. The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer to prevent collisions with other I ...
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... NXP Semiconductors 8.3.4.7 Register read access To read out data from a specific register address in the MFRC523, the host controller must use the following procedure: • Firstly, a write access to the specific register address must be performed as indicated in the frame that follows • The first byte of a frame indicates the device address according to the I • ...
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... NXP Semiconductors 8.3.4.8 High-speed mode In High-speed mode (HS mode), the device can transfer information at data rates 3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard modes (F/S modes) for bidirectional communication in a mixed-speed bus system. 8.3.4.9 High-speed transfer To achieve data rates 3.4 Mbit/s the following improvements have been made to ...
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... NXP Semiconductors S SDA high SCL high Sr SDA high SCL high Master current source pull-up = Resistor pull-up 2 Fig 19. I C-bus HS mode protocol frame 8.3.4.11 Switching between F/S mode and HS mode After reset and initialization, the MFRC523 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected MFRC523 recognizes the “ ...
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... NXP Semiconductors 8.4 Analog interface and contactless UART 8.4.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data ...
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... NXP Semiconductors Table 17. Register and bit settings controlling the signal on pin TX2 Bit Bit Bit Bit Tx1RFEn Force Tx2CW InvTx2RFOn 100ASK [ not care. The following abbreviations have been used in • RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2 • ...
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... NXP Semiconductors 8.4.3 Serial data switch Two main blocks are implemented in the MFRC523. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers possible for the interface between these two blocks to be configured so that the interfacing signals are routed to pins MFIN and MFOUT ...
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TX bit stream MILLER CODER TX serial data stream DIGITAL MODULE MFRC523 RX serial data stream 0 LOW 1 Manchester with subcarrier RX bit stream MANCHESTER 2 internal modulated DECODER UART 3 NRZ coding without subcarrier (> 106 kBd) Sel[1:0] ...
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... NXP Semiconductors 8.4.5 CRC coprocessor The following CRC coprocessor parameters can be configured: • The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg register’s CRCPreset[1:0] bits setting • The CRC polynomial for the 16-bit CRC is fixed to x • ...
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... NXP Semiconductors • FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit • FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit. The MFRC523 can generate an interrupt signal when: • ...
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... NXP Semiconductors The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg. Table 19. Interrupt flag TimerIRq TxIRq CRCIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq 8.7 Timer unit The MFRC523A has a timer unit which the external host can use to manage timing tasks ...
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... NXP Semiconductors The timer can be started manually using the ControlReg register’s TStartNow bit and stopped using the ControlReg register’s TStopNow bit. The timer can also be activated automatically to meet any dedicated protocol requirements, by setting the TModeReg register’s TAuto bit to logic 1. ...
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... NXP Semiconductors for further access to the registers. To ensure this, perform a read access to address 0 until the MFRC523 answers to the last read command with the register content of address 0. This indicates that the MFRC523 is ready. 8.8.3 Transmitter Power-down mode The Transmitter Power-down mode switches off the internal antenna drivers and the RF field. Transmitter Power-down mode is entered by setting either the TxControlReg register’ ...
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... NXP Semiconductors The delay time is calculated by: 1024 t = ------------- - 27 μs d The time (t device activation Fig 23. Oscillator start-up time 9. MFRC523 registers 9.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with same behavior are grouped in common registers. The access conditions are described in Table 20 ...
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... NXP Semiconductors 9.1.1 MFRC523 register overview Table 21. MFRC523 register overview Subaddress Register name (Hex) Page 0: Command and status 00h Reserved 01h CommandReg 02h ComlEnReg 03h DivlEnReg 04h ComIrqReg 05h DivIrqReg 06h ErrorReg 07h Status1Reg 08h Status2Reg 09h FIFODataReg 0Ah FIFOLevelReg 0Bh ...
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... NXP Semiconductors Table 21. MFRC523 register overview Subaddress Register name (Hex) Page 2: Configuration 20h Reserved 21h CRCResultReg 22h CRCResultReg 23h Reserved 24h ModWidthReg 25h Reserved 26h RFCfgReg 27h GsNReg 28h CWGsPReg 29h ModGsPReg 2Ah TModeReg 2Bh TPrescalerReg 2Ch TReloadReg 2Dh TReloadReg 2Eh ...
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... NXP Semiconductors Table 21. MFRC523 register overview Subaddress Register name (Hex) 3Ah TestDAC2Reg 3Bh TestADCReg 3Ch to 3Fh Reserved MFRC523_34 Product data sheet PUBLIC …continued Function defines the test value for TestDAC2 shows the value of ADC I-channel and Q-channel reserved for production tests All information provided in this document is subject to legal disclaimers. Rev. 3.5 — ...
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... NXP Semiconductors 9.2 Register descriptions 9.2.1 Page 0: Command and status 9.2.1.1 Reserved register 00h Functionality is reserved for future use. Table 22. Bit Symbol Access Table 23. Bit Symbol reserved 9.2.1.2 CommandReg register Starts and stops command execution. Table 24. Bit Symbol: Access: Table 25. ...
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... NXP Semiconductors 9.2.1.3 ComIEnReg register Control bits to enable and disable the passing of interrupt requests. Table 26. Bit Symbol Access Table 27. Bit Symbol 7 IRqInv 6 TxIEn 5 RxIEn 4 IdleIEn 3 HiAlertIEn - 2 LoAlertIEn - 1 ErrIEn 0 TimerIEn 9.2.1.4 DivIEnReg register Control bits to enable and disable the passing of interrupt requests. ...
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... NXP Semiconductors 9.2.1.5 ComIrqReg register Interrupt request bits. Table 30. Bit Symbol Access Table 31. All bits in the ComIrqReg register are cleared by software. Bit Symbol 7 Set1 6 TxIRq 5 RxIRq 4 IdleIRq 3 HiAlertIRq 2 LoAlertIRq 1 1 ErrIRq 0 TimerIRq MFRC523_34 Product data sheet PUBLIC ComIrqReg register (address 04h); reset value: 14h bit allocation ...
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... NXP Semiconductors 9.2.1.6 DivIrqReg register Interrupt request bits. Table 32. Bit Symbol Access Table 33. All bits in the DivIrqReg register are cleared by software. Bit Symbol 7 Set2 reserved 4 MfinActIRq 1 3 reserved 2 CRCIRq reserved 9.2.1.7 Status1Reg register Contains status bits of the CRC, interrupt and FIFO buffer. ...
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... NXP Semiconductors Table 35. Bit Symbol 2 reserved 1 HiAlert 0 LoAlert 9.2.1.8 Status2Reg register Contains status bits of the receiver, transmitter and data mode detector. Table 36. Bit Symbol Access Table 37. Bit MFRC523_34 Product data sheet PUBLIC Status1Reg register bit descriptions Value Description - reserved for future use ...
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... NXP Semiconductors Table 37. Bit 9.2.1.9 FIFODataReg register Input and output of 64 byte FIFO buffer. Table 38. Bit Symbol Access Table 39. Bit 9.2.1.10 FIFOLevelReg register Indicates the number of bytes stored in the FIFO. Table 40. Bit Symbol Access Table 41. Bit Symbol 7 FlushBuffer FIFOLevel[6:0] MFRC523_34 Product data sheet ...
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... NXP Semiconductors 9.2.1.11 WaterLevelReg register Defines the level for FIFO under- and overflow warning. Table 42. Bit Symbol Access Table 43. Bit 9.2.1.12 ControlReg register Miscellaneous control bits. Table 44. Bit Symbol Access Table 45. Bit Symbol 7 TStopNow 6 TStartNow reserved RxLastBits[2:0] MFRC523_34 Product data sheet PUBLIC WaterLevelReg register (address 0Bh) ...
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... NXP Semiconductors 9.2.1.13 BitFramingReg register Adjustments for bit-oriented frames. Table 46. Bit Symbol Access Table 47. Bit 9.2.1.14 CollReg register Defines the first bit-collision detected on the RF interface. Table 48. Bit Symbol Access Table 49. Bit Symbol 7 ValuesAfterColl 6 reserved 5 CollPosNotValid MFRC523_34 Product data sheet PUBLIC BitFramingReg register (address 0Dh); reset value: 00h bit allocation ...
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... NXP Semiconductors Table 49. Bit Symbol CollPos[4:0] 9.2.1.15 Reserved register 0Fh Functionality is reserved for future use. Table 50. Bit Symbol Access Table 51. Bit 9.2.2 Page 1: Communication 9.2.2.1 Reserved register 10h Functionality is reserved for future use. Table 52. Bit Symbol Access Table 53. Bit MFRC523_34 Product data sheet ...
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... NXP Semiconductors 9.2.2.2 ModeReg register Defines general mode settings for transmitting and receiving. Table 54. Bit Symbol Access Table 55. Bit MFRC523_34 Product data sheet PUBLIC ModeReg register (address 11h); reset value: 3Fh bit allocation MSBFirst reserved TxWaitRF reserved R/W - R/W ModeReg register bit descriptions ...
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... NXP Semiconductors 9.2.2.3 TxModeReg register Defines the data rate during transmission. Table 56. Bit Symbol Access Table 57. Bit 9.2.2.4 RxModeReg register Defines the data rate during reception. Table 58. Bit Symbol Access Table 59. Bit 7 MFRC523_34 Product data sheet PUBLIC TxModeReg register (address 12h); reset value: 00h bit allocation ...
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... NXP Semiconductors Table 59. Bit 9.2.2.5 TxControlReg register Controls the logical behavior of the antenna driver pins TX1 and TX2. Table 60. Bit Symbol InvTx2RF Access Table 61. Bit Symbol 7 InvTx2RFOn 1 6 InvTx1RFOn 1 5 InvTx2RFOff 1 4 InvTx1RFOff 1 MFRC523_34 Product data sheet PUBLIC RxModeReg register bit descriptions ...
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... NXP Semiconductors Table 61. Bit Symbol 3 Tx2CW 2 reserved 1 Tx2RFEn 0 Tx1RFEn 9.2.2.6 TxASKReg register Controls transmit modulation settings. Table 62. Bit Symbol Access Table 63. Bit Symbol 7 reserved 6 Force100ASK reserved 9.2.2.7 TxSelReg register Selects the internal sources for the analog module. Table 64. Bit Symbol: Access: Table 65 ...
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... NXP Semiconductors Table 65. Bit 9.2.2.8 RxSelReg register Selects internal receiver settings. Table 66. Bit Symbol Access Table 67. Bit MFRC523_34 Product data sheet PUBLIC TxSelReg register bit descriptions Symbol Value Description MFOutSel[3:0] selects the input for pin MFOUT 0000 3-state 0001 LOW 0010 ...
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... NXP Semiconductors 9.2.2.9 RxThresholdReg register Selects thresholds for the bit decoder. Table 68. Bit Symbol Access Table 69. Bit 9.2.2.10 DemodReg register Defines demodulator settings. Table 70. Bit Symbol Access Table 71. Bit MFRC523_34 Product data sheet PUBLIC RxThresholdReg register (address 18h); reset value: 84h bit allocation ...
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... NXP Semiconductors Table 71. Bit 9.2.2.11 Reserved register 1Ah Functionality is reserved for future use. Table 72. Bit Symbol Access Table 73. Bit 9.2.2.12 Reserved register 1Bh Functionality is reserved for future use. Table 74. Bit Symbol Access Table 75. Bit 9.2.2.13 MfTxReg register Controls some MIFARE communication transmit parameters. ...
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... NXP Semiconductors Table 77. Bit 9.2.2.14 MfRxReg register Table 78. Bit Symbol Access Table 79. Bit Symbol reserved 4 ParityDisable reserved 9.2.2.15 TypeBReg register Configures the ISO/IEC 14443 B functionality. Table 80. Bit Symbol Access Table 81. Bit MFRC523_34 Product data sheet PUBLIC MfTxReg register bit descriptions Symbol ...
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... NXP Semiconductors Table 81. Bit 9.2.2.16 SerialSpeedReg register Selects the speed of the serial UART interface. Table 82. Bit Symbol Access Table 83. Bit MFRC523_34 Product data sheet PUBLIC TypeBReg register bit descriptions Symbol Value Description EOFSOFWidth 1 if this bit is set to logic 1 and EOFSOFAdjust bit (AutoTestReg register) is logic 0, the SOF and EOF will have the maximum length defined in ISO/IEC 14443 B ...
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... NXP Semiconductors 9.2.3 Page 2: Configuration 9.2.3.1 Reserved register 20h Functionality is reserved for future use. Table 84. Bit Symbol Access Table 85. Bit 9.2.3.2 CRCResultReg registers Shows the MSB and LSB values of the CRC calculation. Remark: The CRC is split into two 8-bit registers. Table 86. ...
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... NXP Semiconductors 9.2.3.3 Reserved register 23h Functionality is reserved for future use. Table 90. Bit Symbol Access Table 91. Bit 9.2.3.4 ModWidthReg register Sets the modulation width. Table 92. Bit Symbol Access Table 93. Bit 9.2.3.5 Reserved register 25h Functionality is reserved for future use. Table 94. ...
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... NXP Semiconductors 9.2.3.6 RFCfgReg register Configures the receiver gain. Table 96. Bit Symbol Access Table 97. Bit 9.2.3.7 GsNReg register Defines the conductance of the antenna driver pins TX1 and TX2 for the n-driver when the driver is switched on. Table 98. Bit Symbol Access Table 99. ...
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... NXP Semiconductors 9.2.3.8 CWGsPReg register Defines the conductance of the p-driver output during periods of no modulation. Table 100. CWGsPReg register (address 28h); reset value: 20h bit allocation Bit Symbol Access Table 101. CWGsPReg register bit descriptions Bit 9.2.3.9 ModGsPReg register Defines the conductance of the p-driver output during modulation. ...
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... NXP Semiconductors Table 105. TModeReg register bit descriptions Bit Table 106. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation Bit Symbol Access MFRC523_34 Product data sheet PUBLIC Symbol Value Description TAuto 1 the timer starts automatically at the end of the transmission in all communication modes at all speeds or when InvTxnRFOn ...
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... NXP Semiconductors Table 107. TPrescalerReg register bit descriptions Bit 9.2.3.11 TReloadReg register Defines the 16-bit timer reload value. Remark: The reload value bits are contained in two 8-bit registers. Table 108. TReloadReg (higher bits) register (address 2Ch); reset value: 00h bit allocation ...
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... NXP Semiconductors Table 113. TCounterValReg register higher bit descriptions Bit Table 114. TCounterValReg (lower bits) register (address 2Fh); reset value: xxh bit Bit Symbol Access Table 115. TCounterValReg register lower bit descriptions Bit 9.2.4 Page 3: Test 9.2.4.1 Reserved register 30h Functionality is reserved for future use. ...
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... NXP Semiconductors 9.2.4.3 TestSel2Reg register General test signal configuration and PRBS control. Table 120. TestSel2Reg register (address 32h); reset value: 00h bit allocation Bit Symbol Access Table 121. TestSel2Reg register bit descriptions Bit Symbol 7 TstBusFlip 6 PRBS9 5 PRBS15 TestBusSel[4:0] 9.2.4.4 TestPinEnReg register Enables the test bus pin output driver. Table 122. TestPinEnReg register (address 33h) ...
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... NXP Semiconductors 9.2.4.5 TestPinValueReg register Defines the high and low values for the test port when it is used as I/O. Table 124. TestPinValueReg register (address 34h); reset value: 00h bit allocation Bit Symbol Access Table 125. TestPinValueReg register bit descriptions Bit Symbol ...
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... NXP Semiconductors Table 129. AutoTestReg register bit descriptions Bit 9.2.4.8 VersionReg register Shows the MFRC523 software version. Table 130. VersionReg register (address 37h); reset value: xxh bit allocation Bit Symbol Access Table 131. VersionReg register bit descriptions Bit 9.2.4.9 AnalogTestReg register Determines the analog output test signal at, and status of, pins AUX1 and AUX2. Table 132. AnalogTestReg register (address 38h) ...
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... NXP Semiconductors Table 133. AnalogTestReg register bit descriptions Bit Symbol AnalogSelAux1[3: AnalogSelAux2[3:0] - [1] Remark: Current source output; the use of 1 kΩ pull-down resistor on AUXn is recommended. MFRC523_34 Product data sheet PUBLIC Value Description controls pin AUX1 0000 3-state 0001 output of TestDAC1 (AUX1), output of TestDAC2 (AUX2) ...
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... NXP Semiconductors 9.2.4.10 TestDAC1Reg register Defines the test value for TestDAC1. Table 134. TestDAC1Reg register (address 39h); reset value: xxh bit allocation Bit Symbol Access Table 135. TestDAC1Reg register bit descriptions Bit 9.2.4.11 TestDAC2Reg register Defines the test value for TestDAC2. ...
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... NXP Semiconductors 9.2.4.13 Reserved register 3Ch Functionality reserved for production test. Table 140. Reserved register (address 3Ch); reset value: FFh bit allocation Bit Symbol Access Table 141. Reserved register bit descriptions Bit Table 142. Reserved register (address 3Dh); reset value: 00h bit allocation ...
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... NXP Semiconductors 10. MFRC523 command set The MFRC523 operation is determined by a state machine capable of performing a set of commands. A command is executed by writing a command code (see CommandReg register. Arguments and data necessary to process a command are exchanged using the FIFO buffer. 10.1 General description The MFRC523 operation is determined by a state machine capable of performing a set of commands ...
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... NXP Semiconductors Table 148. Command overview Command - MFAuthent SoftReset 10.3.1 MFRC523 command descriptions 10.3.1.1 Idle mode Places the MFRC523 in Idle mode. The Idle command also terminates itself. 10.3.1.2 Mem command Transfers 25 bytes from the FIFO buffer to the internal buffer. To read out the 25 bytes from the internal buffer the Mem command must be started with an empty FIFO buffer ...
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... NXP Semiconductors 10.3.1.6 NoCmdChange command This command does not influence any running command in the CommandReg register. It can be used to manipulate any bit except the CommandReg register Command[3:0] bits, for example, the RcvOff bit or the PowerDown bit. 10.3.1.7 Receive command The MFRC523 activates the receiver path and waits for a data stream to be received. The correct settings must be chosen before starting this command ...
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... NXP Semiconductors Remark: When the MFAuthent command is active all access to the FIFO buffer is blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is set. This command automatically terminates when the MIFARE card is authenticated and the Status2Reg register’s MFCrypto1On bit is set to logic 1. ...
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... NXP Semiconductors 12. Recommended operating conditions Table 150. Operating conditions Symbol Parameter V analog supply voltage DDA V digital supply voltage DDD V TVDD supply voltage DD(TVDD) V PVDD supply voltage DD(PVDD) V SVDD supply voltage DD(SVDD) T ambient temperature amb [1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. ...
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... NXP Semiconductors Table 152. Characteristics …continued Symbol Parameter Conditions Pin SDA I input leakage LI current V HIGH-level input IH voltage V LOW-level input IL voltage [1] Pin RX V input voltage i C input capacitance i V offset R input resistance i V offset Input voltage range; see Figure 24 V minimum Manchester encoded; ...
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... NXP Semiconductors Table 152. Characteristics …continued Symbol Parameter Conditions I HIGH-level output V OH current I LOW-level output V OL current Output characteristics Pin MFOUT V HIGH-level output V OH voltage V LOW-level output V OL voltage I LOW-level output V OL current I HIGH-level output V OH current Pin IRQ V HIGH-level output ...
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... NXP Semiconductors Table 152. Characteristics …continued Symbol Parameter Conditions V LOW-level output V OL voltage I CWGsP[5:0] = 0Fh V I CWGsP[5:0] = 0Fh V I CWGsP[5:0] = 0Fh V I CWGsP[5:0] = 0Fh Current consumption I power-down current digital supply pin DVDD; V DDD current I analog supply pin AVDD; V DDA current CommandReg register’s bit RcvOff = 0 pin AVDD ...
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... NXP Semiconductors Table 152. Characteristics …continued Symbol Parameter Conditions Typical input requirements f crystal frequency xtal ESR equivalent series resistance C load capacitance L P crystal power xtal dissipation [1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD. [ the total current for all supplies. ...
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... NXP Semiconductors Table 153. SPI timing characteristics Symbol t h(SCKL-Q) t (SCKL-NSSH) t NSSH Table 154. I Symbol Parameter f SCL t HD;STA t SU;STA t SU;STO t LOW t HIGH t HD;DAT t SU;DAT BUF MFRC523_34 Product data sheet PUBLIC …continued Parameter Conditions SCK LOW to data output SCK to changing MISO hold time ...
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... NXP Semiconductors SCK MOSI MISO NSS Fig 25. Timing diagram for SPI SDA SCL Fig 26. Timing for Fast and Standard mode devices on the I MFRC523_34 Product data sheet PUBLIC t t SCKL SCKH t t DXSH SHDX MSB MSB Remark: The signal NSS must be LOW to be able to send several bytes in one data stream. ...
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... NXP Semiconductors 15. Application information A typical application diagram using a complementary antenna connection to the MFRC523 is shown in The antenna tuning and RF part matching is described in the application note Ref. 2. MICRO- PROCESSOR Fig 27. Typical application diagram MFRC523_34 Product data sheet PUBLIC Figure 27. supply DVDD AVDD TVDD ...
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... NXP Semiconductors 16. Test information 16.1 Test signals 16.1.1 Self-test The MFRC523 has the capability to perform a digital self-test. The self-test is started by using the following procedure: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and implement the Config command. 3. Enable the self-test by writing 09h to the AutoTestReg register. ...
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... NXP Semiconductors Table 156. Test bus signals: TestBusSel[4:0] = 0Dh Pins 16.1.3 Test signals on pins AUX1 or AUX2 The MFRC523 allows the user to select internal signals for measurement on pins AUX1 or AUX2. These measurements can be helpful during the design-in phase to optimize the design or used for test purposes. ...
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... NXP Semiconductors (1) TestDAC1 (500 mV/div) on pin AUX1. (2) TestDAC2 (500 mV/div) on pin AUX2. Fig 28. Output test signals TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2 16.1.3.2 Example: Output test signals Corr1 and MinLevel Figure 29 The AnalogTestReg register is set to 24h. (1) MinLevel (1 V/div) on pin AUX2. ...
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... NXP Semiconductors 16.1.3.3 Example: Output test signals ADC I-channel and ADC Q-channel Figure 30 AUX2, respectively. The AnalogTestReg register is set to 56h. (1) ADC_I (1 V/div) on pin AUX1. (2) ADC_Q (500 mV/div) on pin AUX2. (3) RF field. Fig 30. Output ADC I-channel on pin AUX1 and ADC Q-channel on pin AUX2 16 ...
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... NXP Semiconductors (1) RxActive (2 V/div) on pin AUX1. (2) TxActive (2 V/div) on pin AUX2. (3) RF field. Fig 31. Output RxActive on pin AUX1 and TxActive on pin AUX2 16.1.3.5 Example: Output test signal RX data stream Figure 32 register’s TestBusSel[4:0] bits are set to 07h to enable test bus signals on pins D1 to D6; ...
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... NXP Semiconductors 16.1.3.6 Pseudo-Random Binary Sequences (PRBS) The pseudo-random binary sequences PRBS9 and PRBS15 are based on ITU-TO150 and are defined with the TestSel2Reg register. Transmission of either data stream is started by the Transmit command. The preamble/sync byte/start bit/parity bit are automatically generated depending on the mode selected. ...
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... NXP Semiconductors 17. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area terminal 1 index area 32 DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors Detailed package information can be found at: 18. Handling information Moisture Sensitivity Level (MSL) evaluation has been performed according to SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C). MSL for this package is level 1 which means 260 °C convection reflow temperature. Dry pack is not required. Unlimited out-of-pack floor life at maximum ambient 30 °C/85 % RH. ...
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... NXP Semiconductors The straps around the package of stacked trays inside the piano-box have sufficient pre-tension to avoid loosening of the trays. chamfer PIN 1 chamfer PIN 1 printed piano box Fig 35. Packing information 5 trays MFRC523_34 Product data sheet PUBLIC strap 46 mm from corner All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 20. Abbreviations Table 158. Abbreviations Acronym ADC ASK BPSK CRC CW DAC EOF ETU HBM LSB MISO MM MOSI MSB NRZ NSS PCB PLL PRBS RX SOF SPI TX UART 21. Glossary Modulation index — Defined as the voltage ratio (V Load modulation index — Defined as the voltage ratio for the card − ...
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... NXP Semiconductors 23. Revision history Table 159. Revision history Document ID Release date MFRC523_35 20100924 • Modifications: Table 131 “VersionReg register bit descriptions” on page 63 MFRC523_34 20100715 • Modifications: Section 9.2.2.10 “DemodReg register”: register updated. • Section 9.2.2.15 “TypeBReg register”: register updated. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 26. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 4. Communication overview for ISO/IEC 14443 A reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Table 5. Connection protocol for detecting different interface types . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 6. MOSI and MISO byte order . . . . . . . . . . . . . . . 11 Table 7. MOSI and MISO byte order . . . . . . . . . . . . . . . 11 Table 8. ...
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... NXP Semiconductors reset value: 84h bit allocation . . . . . . . . . . . . .50 Table 69. RxThresholdReg register bit descriptions . . . .50 Table 70. DemodReg register (address 19h); reset value: 4Dh bit allocation . . . . . . . . . . . . .50 Table 71. DemodReg register bit descriptions . . . . . . . . .50 Table 72. Reserved register (address 1Ah); reset value: 00h bit allocation . . . . . . . . . . . . .51 Table 73. Reserved register bit descriptions . . . . . . . . . .51 Table 74. Reserved register (address 1Bh) ...
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... NXP Semiconductors Table 133. AnalogTestReg register bit descriptions . . . . .64 Table 134. TestDAC1Reg register (address 39h); reset value: xxh bit allocation . . . . . . . . . . . . .65 Table 135. TestDAC1Reg register bit descriptions . . . . . .65 Table 136. TestDAC2Reg register (address 3Ah); reset value: xxh bit allocation . . . . . . . . . . . . .65 Table 137. TestDAC2Reg register bit descriptions . . . . . .65 Table 138. TestADCReg register (address 3Bh) ...
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... NXP Semiconductors 27. Figures Fig 1. Simplified block diagram of the MFRC523 Fig 2. Detailed block diagram of the MFRC523 . . . . . . . .5 Fig 3. Pinning configuration HVQFN32 (SOT617- Fig 4. MFRC523 Read/Write mode . . . . . . . . . . . . . . . . .8 Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram Fig 6. Data coding and framing according to ISO/IEC 14443 Fig 7. ...
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... NXP Semiconductors 28. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Functional description . . . . . . . . . . . . . . . . . . . 8 8.1 ISO/IEC 14443 A functionality . . . . . . . . . . . . . 8 8.2 ISO/IEC 14443 B functionality . . . . . . . . . . . . . 9 8.3 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . 9 8 ...
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... NXP Semiconductors 9.2.3.3 Reserved register 23h . . . . . . . . . . . . . . . . . . 55 9.2.3.4 ModWidthReg register . . . . . . . . . . . . . . . . . . 55 9.2.3.5 Reserved register 25h . . . . . . . . . . . . . . . . . . 55 9.2.3.6 RFCfgReg register . . . . . . . . . . . . . . . . . . . . . 56 9.2.3.7 GsNReg register . . . . . . . . . . . . . . . . . . . . . . . 56 9.2.3.8 CWGsPReg register . . . . . . . . . . . . . . . . . . . . 57 9.2.3.9 ModGsPReg register . . . . . . . . . . . . . . . . . . . 57 9.2.3.10 TModeReg and TPrescalerReg registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2.3.11 TReloadReg register . . . . . . . . . . . . . . . . . . . 59 9.2.3.12 TCounterValReg register . . . . . . . . . . . . . . . . 59 9.2.4 Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.4.1 Reserved register 30h . . . . . . . . . . . . . . . . . . 60 9 ...