XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet
XR17V352IB-0A-EVB
Specifications of XR17V352IB-0A-EVB
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XR17V352IB-0A-EVB Summary of contents
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SEPTEMBER 2010 GENERAL DESCRIPTION 1 The XR17V352 (V352 single chip 2-channel PCI Express (PCIe) UART (Universal Asynchronous Receiver and Transmitter), optimized for higher performance and lower power. The V352 serves as a single lane PCIe bridge to 2 ...
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... GND F GND GND REXT TX+ TX- GND G H GND VCC12 VCC33 J CLKREQ# PERST# MPIO9 MPIO7 MPIO8 MPIO11 K NC MPIO10 MPIO12 L ORDERING INFORMATION ART UMBER ACKAGE XR17V352IB113-F 113-FPBGA Transparent Top View GND NC TMRCK TEST2 NC NC ENIR# TEST1 NC NC EN485# FB GND VCC33 GND VCC12 ...
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REV. 1.0.1 PIN DESCRIPTIONS AME IN YPE PCIe SIGNALS CLK+ E4 CLK RX+ E1 RX- E2 CLKREQ PERST# J2 REXT F3 MODEM OR SERIAL I/O INTERFACE TX0 ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART PIN DESCRIPTIONS AME IN YPE MPIO SIGNALS MPIO0 A2 I/O MPIO1 C3 I/O MPIO2 B2 I/O MPIO3 B1 I/O MPIO4 C2 I/O MPIO5 D3 I/O MPIO6 C1 I/O MPIO7 ...
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REV. 1.0.1 PIN DESCRIPTIONS AME IN YPE EEDI J8 O EEDO L9 JTAG SIGNALS TRST# L6 TCK K6 TMS J6 TDI L7 TDO K7 O BUCK REGULATOR SIGNALS ENABLE C10 A10 O ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART PIN DESCRIPTIONS AME IN YPE VCC33B B10, B11 Pwr VCC12 D7, G8, H5 Pwr VCC12A H2 Pwr GND A4, A8, B8, C8, Pwr D1, D4, D6, D8, D11, E3, ...
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REV. 1.0.1 FUNCTIONAL DESCRIPTION The XR17V352 (V352) integrates the functions of two independent enhanced 16550 UARTs, a general purpose 16-bit timer/counter, and 16 multi-purpose I/Os (MPIOs). Each UART channel has its own 16550 UART compatible configuration register set for individual ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 1.0 XR17V352 INTERNAL REGISTERS The XR17V352 UART register set is very similar to the previous generation PCI UARTs. This makes the V352 software compatible with the previous generation PCI UARTs. Minimal changes are ...
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REV. 1.0 PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x00 31:16 EWR Device ID 15:0 EWR Vendor ID (Exar) specified by PCISIG 0x04 31 RWC Parity error detected. Cleared by writing a logic 1. ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART T 1: PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x18h 31:0 RO Unimplemented Base Address Register (returns zeros) 0x1C 31:0 RO Unimplemented Base Address Register (returns zeros) 0x20 31:0 ...
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REV. 1.0 PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x80 31:16 RO PCI Express 2.0 capable endpoint, Interrupt Message Number 1 15:8 RO Next Capability Pointer 7:0 RO PCI Express Capability ID 0x84 31:16 ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART T 1: PCI L ABLE A DDRESS B T ITS YPE O FFSET 0x104- 31:0 RO Not implemented or not applicable (return zeros) 0x113 0x114 31 Offset 0x4 N : EWR=Read/Write ...
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REV. 1.0.1 1.3 Device Internal Register Sets The Device Configuration Registers and the two individual UART Configuration Registers of the V352 occupy 2K of PCI bus memory address space. These addresses are offset onto the basic memory address, a value ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART T 4: XR17V352 UART ABLE FFSET DDRESS EMORY 0x0000 - 0x000F UART channel 0 Regs 0x0010 - 0x007F Reserved 0x0080 - 0x009A DEVICE CONFIGURATION REGISTERS 0x009B - 0x00FF Reserved 0x0100 ...
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REV. 1.0.1 1.4 Device Configuration Registers The Device Configuration Registers provide easy programming of general operating parameters to the V352 and for monitoring the status of various functions. These registers control or report on both channel UARTs functions that include ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART ABLE EVICE A [A7:A0] R DDRESS EGISTER Ox098 MPIOINV[15:8] Ox099 MPIOSEL[15:8] 0x09A MPIOOD[15:8] 0x09B Reserved ABLE EVICE A R DDRESS EGISTER - INTERRUPT (read-only) 0x0080 0x0083 ...
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REV. 1.0.1 INT0 [7:0] Channel Interrupt Indicator Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and bit [1] indicates channel 1. All other bits are reserved. Logic 1 indicates the ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART T ABLE Wake-up Indicator is cleared by reading the INT0 register. RXRDY and RXRDY Time-out is cleared by reading data in the RX FIFO. RX Line Status interrupt clears after reading the LSR ...
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REV. 1.0.1 16-Bit Timer/Counter Programmable Registers TIMERMSB Register Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 REGA [15:8] Register Reserved. TIMERCNTL [7:0] Register The bits [3:0] of this register are used to issue commands. The commands are self-clearing, so reading this register ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART TIMER OPERATION The following paragraphs describe the operation of the 16-bit Timer/Counter. The following conventions will be used in this discussion: ’N’ is the 16-bit value programmed in the TIMER MSB, LSB registers ...
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REV. 1.0 IGURE IMER UTPUT IN NE HOT AND START TIMER COMMAND ISSUED TIMER Output in One-Shot Mode < 'N' Clocks After 'P' TIMER Output in clocks Re-triggerable Mode Timer Interrupt In the one-shot ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 8X sampling rate. Transmit and receive data rates will double by selecting 8X. If using the 4XMODE, the corresponding bit in this register should be logic 0 1.4.4 4XMODE [15:8] (default 0x00) Each ...
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REV. 1.0.1 The 8-bit SLEEP register enables each UART separately to enter Sleep mode. The SLEEP register is accessible from the Device Configuration Registers in all UART channels but the UART channel can only control the bit for that channel. ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 1.4.7 REGB Register REGB[18](Read/Write Logic 0 (default) - Global interrupt enable. Interrupts to PCI host are enabled. Logic 1 - Global interrupt disable. Interrupts to PCI host are disabled. REGB[19](Read-Only) Logic 0 - ...
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REV. 1.0.1 There are 2 sets of 6 registers that select, control and monitor the 16 multipurpose inputs and outputs. Figure 8 shows the internal circuitry IGURE ULTIPURPOSE NPUT UTPUT ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART MPIOINT [15:0] (default 0x00) The MPIOINT register enables the multipurpose input pin interrupt MPIO pin is selected by MPIOSEL as an input, then it can be selected to generate an interrupt. ...
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REV. 1.0.1 MPIOSEL [15:0](default 0xFF) The MPIOSEL register defines the MPIOs as either an input or output. A logic 1 (default) defines the pin for input and a logic 0 for output. Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 2.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data register for ...
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REV. 1.0.1 Channel Receive Data in 32-bit alignment through the Configuration Register Address Receive Data Byte n PCI Bus Data Bit-31 ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART Channel Transmit Data in 32-bit alignment through the Configuration Register Address Transmit Data Byte n ...
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REV. 1.0.1 3.0 UART There are 2 UARTs channel [1:0] in the V352. Each has its own 256-byte of transmit and receive FIFO, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART IGURE AUD ATE ENERATOR 125 MHz Clock (Master) or 62.5 MHz Clock (Slave) To Other Channel DLL, DLM and DLD Registers MCR Bit-7=0 Prescaler (default) Divide by 1 ...
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REV. 1.0.1 T 11: T ABLE YPICAL DATA RATES WITH R D EQUIRED IVISOR FOR O D 16x Clock O UTPUT ATA R (Decimal) ATE 2400 3255.21 4800 1627.60 9600 813.80 10000 781.25 19200 406.90 25000 312.5 28800 271.27 38400 ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 3.2 Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Operation Automatic hardware or RTS/DTR and CTS/DSR flow control is used to prevent data overrun to the local receiver FIFO and remote receiver FIFO. The ...
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REV. 1.0.1 F 10. A RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts 4 ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 3.3 Infrared Mode Each UART in the V352 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.1. The input pin ENIR conveniently activates both UART channels to ...
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REV. 1.0.1 3.4 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit [ logic 1. All regular UART functions operate normally. Figure 12 ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 3.5 UART CHANNEL CONFIGURATION REGISTERS Address lines select the 16 registers in each channel. The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper ...
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REV. 1.0.1 T 13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD B [7] IT A3- AME RITE RHR R BIT [ THR W BIT ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART T 13: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD B [7] IT A3- AME RITE EFR R/W Auto CTS/ DSR Enable ...
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REV. 1.0 IGURE RANSMITTER PERATION IN NON ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 3.7 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every ...
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REV. 1.0.1 3.7.2 Receiver Operation with FIFO F 16 IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) 256 bytes by 11-bits wide FIFO Receive Data Receive Data Byte and Errors 3.7.3 ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 4.0 UART CONFIGURATION REGISTERS 4.1 Receive Holding Register (RHR) - Read only SEE”RECEIVER” ON PAGE 42. 4.2 Transmit Holding Register (THR) - Write only SEE”TRANSMITTER” ON PAGE 40. 4.3 Baud Rate Generator Divisors ...
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REV. 1.0.1 4.4.2 IER versus Receive/Transmit FIFO Polled Mode Operation When FCR bit [0] equals a logic 1 for FIFO enable; resetting IER bits [3:0] enables the XR16V352 in the FIFO polled mode of operation. Since the receiver and transmitter ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART IER[1]: TX Ready Interrupt Enable In non-FIFO mode interrupt is issued whenever the THR is empty. In the FIFO mode, an interrupt is issued twice: once when the number of bytes ...
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REV. 1.0.1 • Wake-up indicator is cleared by a read to the INT0 register ABLE P ISR R RIORITY EGISTER L B [5] B [4] B [3] EVEL ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART FCR[3]: DMA Mode Select This bit has no effect since TXRDY and RXRDY pins are not available in this device provided for legacy software compatibility. • Logic 0 = Set DMA ...
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REV. 1.0.1 T 15: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER T BIT [7] BIT [6] BIT [7] ABLE Table Table 4.7 Line Control Register (LCR) - Read/Write The ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART LCR BIT [5] LCR BIT [ LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit [3] set to a logic 1, LCR ...
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REV. 1.0.1 MCR[7]: Clock Prescaler Select (requires EFR bit [4]=1) • Logic 0 = Divide by one. The internal 125MHz clock is fed directly to the Programmable Baud Rate Generator without further modification, i.e., divide by one (default). • Logic ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART MCR[2]: DTR# or RTS# for Auto Flow Control (OP1 in Local Loopback Mode) DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by ...
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REV. 1.0.1 LSR[3]: Receive Data Framing Error Flag • Logic framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART MSR[3]: Delta CD# Input Flag • Logic change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was ...
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REV. 1.0.1 T 17: A RS485 H ABLE UTO ALF MSR[7] MSR[ MSR [3]: Transmitter Disable This bit can be used to disable the ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART MSR [2]: Receiver Disable This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to a logic 1, the receiver will operate ...
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REV. 1.0.1 FCTR[5]: Auto RS485 Enable Auto RS485 half duplex control enable/disable. RTS# or DTR# can be selected as the control output via MCR bit-2. Note that this feature has precedence over the Auto RTS/DTR flow control feature (EFR bit-6). ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 4.14 Enhanced Feature Register (EFR) - Read/Write Enhanced features are enabled or disabled using this register. Bits [3:0] provide single or dual consecutive character software flow control selection (see are selected, the double ...
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REV. 1.0.1 EFR[3:0]: Software Flow Control Select Combinations of software flow control can be selected by programming these bits, as shown in T ABLE EFR BIT [3] EFR BIT [2] EFR BIT [ ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART 4.18 RXTRG[7:0]: Receive FIFO Trigger Level - Write Only An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0xFF (255). The RX FIFO trigger level ...
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REV. 1.0.1 REGISTERS RESET STATE DLL Bits [7:0] = 0x01 DLM Bits [7:0] = 0x00 DLD Bits [7:0] = 0x00 RHR Bits [7:0] = 0xXX THR Bits [7:0] = 0xXX IER Bits [7:0] = 0x00 FCR Bits [7:0] = 0x00 ...
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XR17V352 HIGH PERFORMANCE DUAL PCI EXPRESS UART ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (113-FPBGA) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS O O TA=-40 + INDUSTRIAL GRADE ...
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REV. 1.0.1 PACKAGE DIMENSIONS (113-FPBGA) Seating Plane N : Note: The control dimension is the millimeter column OTE SYMBOL HIGH PERFORMANCE DUAL PCI EXPRESS UART ...
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... September 2010 Rev 1.0.1 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...