AT42QT2161-MMU Atmel, AT42QT2161-MMU Datasheet

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... Applications: laptop, mobile, consumer appliances, PC peripheral etc. ® • Patents: AKS (patented Adjacent Key Suppression) technology ® QMatrix (patented charge-transfer method) ® QSlide (patented charge-transfer method) (patent-pending QSlide sensing configuration) • This datasheet is applicable to revision 1.0 chips only QSlide, 16-key QMatrix Sensor IC AT42QT2161 2 C-compatible 9614A–AT42–08/10 ...

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... Pinout and Schematic 1.1 Pinout Configuration GPIO2 GPIO3 CHANGE 1.2 Pin Description Table 1-1. Pin AT42QT2161 VDD QT2161 4 VSS Pin Listing Function I/O GPIO2 I/O General purpose input/output 2 GPIO3 I/O General purpose input/output 3 Vdd P Vss CHANGE OD State change notification Vref P SMP ...

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... Y0A I/O Y line connection Y1A I/O Y line connection GPIO1 I/O General purpose input/output 1 I Input only O Output only, push-pull OD Open drain output AT42QT2161 If Unused, Comments Connect To... Leave open Leave open – – – Leave open Leave open – – – – ...

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... Section 3.11 on page • Section 5.4 on page • Section 3.2 on page • Section 3.2 on page AT42QT2161 4 follow regulator manufacturer’s recommended values for input and output bypass capacitors. VDD tightly wire a 100 nF bypass capacitor between Vdd and Vss (pins 3 and 4). QT2161 ...

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... Introduction 9614A–AT42–08/10 Inputs/Outputs The AT42QT2161-MMU (QT2161 digital burst mode charge-transfer (QT sensor designed specifically for matrix layout touch controls. It can use keys and a slider (constructed from 2 – 8 keys). There are three dedicated General Purpose Input/Outputs (GPIOs) which can be used as inputs for mechanical switches etc driven outputs. There are eight shared General Purpose Outputs (GPOs) (X0 – ...

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... Y0. The slider can consist of a minimum of 2 keys and a maximum of 8 keys. 2.3 Enabling/Disabling Keys Keys can be enabled by setting a nonzero burst length. A zero burst length disables the key. AT42QT2161 6 The QT2161 includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions. Only a few external parts are required for operation ...

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... The burst length directly impacts key gain; each key can have a unique burst length in order to allow tailoring of key sensitivity on a key-by-key basis. 9614A–AT42–08/10 Table 3-1 shows the key numbering. Key Numbers (Section 3.2 on page 8); this can be set on a per-key basis. A burst is completed AT42QT2161 Key numbers 7 ...

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... high count and watching what the waveform does as it descends towards and below -0.25V. The waveform will appear deceptively straight, but it will slowly start to flatten even before the -0.25V level is reached. A correct waveform is shown in substantially straight (ignoring the downward spikes). AT42QT2161 8 Section 3.4. shows a defective waveform similar to that of Figure 3-3 ...

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... Figure 3-3. 9614A–AT42–08/10 VCs – Nonlinear During Burst (Burst too long too small, or X-Y transcapacitance too large) X Drive YnB VCs – Poor Gain, Nonlinear During Burst (Excess capacitance from Y line to Gnd) X Drive YnB VCs – Correct X Drive YnB AT42QT2161 9 ...

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... The upper limits of Rx and Ry are reached when the signal level and hence key sensitivity are clearly reduced. The limits of Rx and Ry will depend on key geometry and stray capacitance, and thus an oscilloscope is required to determine optimum values of both. AT42QT2161 10 Drive Pulse Roll-off and Dwell Time ...

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... Where the panels are thin (under 2 mm thick) the electrode density can be quite high. 9614A–AT42–08/10 10). Increasing Rx values will cause the leading edge of the X pulses to increasingly roll (Figure 3-5). Only one key along a particular X line needs to be Probing X-Drive Waveforms With a Coin AT42QT2161 (Figure 3-4 Figure 3-6. Figure 3-6 can be used. ...

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... Stability of the reported position will be dependent on the amount of signal on the slider keys. Running at higher resolutions, with a thick panel might produce a fluctuating reported position. AT42QT2161 12 Recommended Key Structure X0 “ ...

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... PCB layer furthest away from the plane/flood, to reduce parasitic capacitance. Cross-hatched ground patterns can act as effective shields, while helping to reduce parasitic capacitance. Ground planes/floods around the chip are generally acceptable, taking into account the same con- siderations as for the Y line parasitics. AT42QT2161 13 ...

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... A standard inexpensive Low Dropout (LDO) type regulator should be used that is not also used to power other loads such as LEDs, relays, or other high current devices. Load shifts on the output of the LDO can cause Vdd to fluctuate enough to cause false detection or sensitivity shifts. AT42QT2161 14 Position of Tracks Example of g ...

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... The pin is active low, and a low pulse lasting at least 10µs must be applied to this pin to cause a reset external hardware reset is not used, the reset pin may be connected to Vdd. 9614A–AT42–08/10 by the user OR reference value plus three-quarters of the negative threshold OR AT42QT2161 15 ...

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... RST pin mode is set. If the Wake option is set for the dedicated GPIO inputs, then the QT2161 will trigger the CHANGE line if a change in status (either positive or negative going edge) of the respective GPIO is detected, in SLEEP mode. AT42QT2161 16 Section 3.2 on page 8 ...

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... The dedicated GPIOs have a Wake option, that if enabled will enable dedicated GPIOs set as inputs read in SLEEP mode. Note that shared GPOs (X0 – X7) are driven by the burst pulses during acquisition bursts, if the corresponding X line is used in the keys/slider. A low pass filter can be inserted to eliminate these burst pulses, as shown in 9614A–AT42–08/10 Figure 1-2 on page 5. AT42QT2161 17 ...

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... Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high; The only exception to this rule is for generating START and STOP conditions. AT42QT2161 18 2 -compatible bus protocol is available from ...

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... Data Transfer SDA SCL Data Stable 4-3, START and STOP conditions are signaled by changing the level of the SDA line START and STOP Conditions SDA SCL START AT42QT2161 Data Stable Data Change STOP 19 ...

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... ACK of transfer. If SCL or SDA is continuously held low for more than ~12 ms, this will be deemed as a error condition and the Note: Each write or read cycle must end with a STOP condition. The QT2161 may not respond correctly if a cycle is terminated by a new START condition. AT42QT2161 20 Address Packet Format Addr MSB ...

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... Note that several data bytes can be transmitted Data Packet Format Data MSB 1 2 SLA+R/W Packet Transmission Addr MSB Addr LSB R/W ACK SLA+R/W AT42QT2161 Data LSB ACK STOP or Data Byte Next Data Byte Data MSB Data LSB ACK ...

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... Write-bit. The device sends an ACK. The host then sends the memory address within the device it wishes to write to. The device sends an ACK. The host transmits one or more data bytes; each will be acknowledged by the device. AT42QT2161 22 2 ...

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... SLA+W A MemAddress Data 2 Data 1 A -compatible bus transmits data and clock with SDA and SCL. They are open-drain; that is 2 C-compatible specifications (1µs maximum). Section 9.4 on page 45). Anything faster will not provide new information and AT42QT2161 Device to Host A S SLA Data -compatible device is pulling it down ...

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... Communications Protocol 6.1 Introduction The device is address mapped. All communications consist of writes to, and reads from, locations in an 8-bit address map. Table 6-1. AT42QT2161 24 Table 6-1 Memory Map Address 0 Chip ID 1 Major/minor code version 2 General Status 3 Key Status 1 4 Key Status 2 5 Slider Touch Position ...

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... Common change Keys 2 – 80 – 99 Reserved 0x00 – 100 – 131 Key 0 15 Signals – 132 – 163 Key 0 15 References Chip Code Version Major Version AT42QT2161 Use Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Chip Minor Version Access – Read ...

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... Address 3: detect status for keys Address 4: detect status for keys Each location indicates all keys in detection, if any bitfield; touched keys report as “1”, untouched or disabled keys report as “0”. A change in this byte will cause the CHANGE line to trigger. AT42QT2161 26 General Status b7 b6 ...

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... This is an 8-bit sub-revision number that follows the code version (e.g. 1.0.0). 6.9 Address 10: Calibrate Table 6-9. Address 10 Writing any nonzero value into this address will trigger the QT2161 to start a recalibration on all enabled keys. 9614A–AT42–08/10 Slider Touch Position GPIO Read GPIO3 Sub-revision Calibrate AT42QT2161 Position GPIO2 GPIO1 Sub-revision CALIBRATE ...

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... The number of burst repetitions can be reduced in low noise environments for faster response time. The BREP value can range between 1 – 63 repetitions. Do not set to 0 because it is not valid. Default value:1 (one measurement burst) AT42QT2161 28 Reset b7 b6 ...

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... Neg/Pos Drift Compensation Figure 6-1) is performed by making the reference level track the raw Thresholds and Drift Compensation Reference Hysteresis Threshold Signal Output AT42QT2161 NDRIFT PDRIFT b0 29 ...

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... Default value) 6.15 Address 18: Negative Recal Delay Table 6-15. Address object unintentionally contacts a key resulting in a detection for a prolonged interval it is usually desirable to recalibrate the key in order to restore its function, perhaps after a time delay of some seconds. AT42QT2161 30 Detect Integrator Negative Recal Delay ...

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... Values of 0 and 1 are invalid and should not be used. Note recommended having a DHT/AWAKE of at least two seconds to prevent unintended key sensitivity drifts and the slider being unresponsive in longer LP modes. DHT/AWAKE Default: 25 (4s) 9614A–AT42–08/10 Drift Hold Time/Awake Timeout AT42QT2161 DHT/AWAKE b0 31 ...

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... Note: For better stability of the reported position at higher resolutions, increase the number of keys used to construct the slider, reduce the front panel thickness, reduce the loading on the slider keys or increase the burst length to gain more signal. Default bits) AT42QT2161 32 Slider Control b7 b6 ...

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... The QT2161 uses a fixed number of pulses which are executed in burst mode. This number is set in groups of four. Therefore, the value send to the QT2161 is multiplied by four to get the actual number of burst pulses. 9614A–AT42–08/10 Key Control Section 3.9.2 on page 13). Negative Threshold Burst Length BURST LENGTH AT42QT2161 AKS GROUP THRESHOLD ...

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... X lines, make sure that the driven device will not be affected. Default: 0 (All driven low) 6.23 Address 73: GPIO Direction Table 6-24. Address 73 Sets the direction of the GPIOs driven outputs floating inputs. If set as inputs, the GPIO will only be read every 16 ms (fixed cycle time). AT42QT2161 34 GPIO/GPO Drive ...

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... A value of 0 – 10 gives a 100 percent low output • A value of 250 – 255 gives a 100 percent high output Default: 0 (100 percent low output) 9614A–AT42–08/10 GPIO/GPO PWM GPIO3 PWM Level AT42QT2161 GPIO2 GPIO1 DUTY_CYC ...

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... These are the key’s 16-bit reference which is accessed as two 8-bit bytes, stored LSB first. There are a total of 16 keys and 4 bytes of data per key, yielding a total of 64 addresses. These addresses are read-only. Table 6-29. Address 100 101 102 103 104 – 131 AT42QT2161 36 GPIO Wake GPIO3 Common Change Keys ...

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... Slider RESOLUTIO – Slider N – KEY_CONT – NTHR 1 255 8 – 255 8 AT42QT2161 Default Value Description 0: SLEEP mode (no capacitive sensing 255: Low Power mode, increments in steps – Range burst repetitions Range is in 0.16s increments 0.16s/reference level Range is in 0.16s increments 0.16s/reference level ...

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... Table 7-1. Setups Table (continued) Address Bytes Parameter 70 1 GPO Drive GPIO Drive GPIO Direction AT42QT2161 38 Valid Key Symbol Range Bits Scope – – – – – – – – – GPIO3 – GPIO2 – GPIO1 – GPIO3 – GPIO2 – ...

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... DUTY_CYC 0 255 8 GPIOs - - – GPIO3 – GPIO2 – GPIO1 – – k0 k15 AT42QT2161 Default Value Description - PWM disabled 1: PWM enabled - GPIO set to output PWM disabled - 0 1: PWM enabled - PWM enabled, – 0 10: 100 percent low output 0 – 250 255: 100 percent high ...

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... The CHANGE line will remain active until the status location containing the status for that key is read. If the CHANGE line does not go low then it is likely the sensitivity of the key is not high enough. The burst length should be increased to increase the sensitivity. AT42QT2161 40 Section 8 ...

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... AKS technology will lock out anything else in the same AKS group. Similarly, a key in the same AKS group as the slider can lock out the slider as a whole object. Note: for normal operation all keys in the slider should be placed in the same AKS group. 9614A–AT42–08/10 8) will also help. AT42QT2161 41 ...

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... proceed to the next step. 8. Repeat steps 5, 6 and 7. Steps 5 and 6 are the continuous normal operating loop sequence after initialization. AT42QT2161 42 shows a summary of the GPIO options, and the precedence of each setting. GPIO Options Wake ...

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... Read all status bytes (Address 2 – restore CHANGE pin to inactive CHANGE pin active (low)? Read required Status bytes and other status bytes that changed , to restore CHANGE pin to inactive (high). Host processes received status bytes Yes ‘Reset occurred’ bit = 1? AT42QT2161 No Yes (high) No Yes No 43 ...

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... Supply ripple+noise* (<1 MHz) Supply ripple+noise* (>1 MHz) Cx transverse load capacitance per key Note: *Applicable to QT2161 on a typical setup, with Burst Repetition (BREP The effects of supply ripple and noise on performance is more prominent the nearer the burst center frequency. AT42QT2161 44 -0.5 to +6V ±10 mA infinite infinite -0 ...

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... Min Typ 40 80 – 120 160 – 400 – ±8 – 250 – 1000 – 25 AT42QT2161 Max Units Notes – µA Vdd = 3.3V Vdd = 1.8V – µA Vdd = 3.3V Vdd = 5.0V 3500 µA Vdd = 3.3V 0.2Vdd V 1.8V <Vdd <5V – ...

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... Power Consumption Table 9-1. AT42QT2161 46 Average Current Consumption Test condition: 16 keys enabled actual pulses), BREP = 1 LP Mode SLEEP 128 ms LP 256 ms LP 512 ms LP 1024 ms Idd (µA) at Vdd = 3.3V <2 µA 1141.03 920.51 810.26 755.13 727.56 713.78 706.89 9614A–AT42–08/10 ...

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... Package Drawing Contact: packagedrawings@atmel.com 9614A–AT42–08/ TITLE 28M1, 28-pad 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 x 2.4 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) AT42QT2161 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 0.80 0.90 1 ...

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... LOTCODE (for traceability) 28 Pin 2161 Abbreviation of Part Number 1R0 Code revision (1.0 released) Date Code Description W=Week code Abbreviation of Part Number AT42QT2161-MMU Date Code W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...Z=52 9614A–AT42–08/10 ...

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... Part Number Part Number AT42QT2161-MMU 9.9 Moisture Sensitivity Level (MSL) MSL Rating 9614A–AT42–08/10 Description 28-pin MLF RoHS compliant IC Peak Body Temperature MSL3 260 AT42QT2161 Specifications o C IPC/JEDEC J-STD-020C 49 ...

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... Associated Documents • Application Note – Touch Sensors Design Guide Revision History Revision No. Revision A – August 2010 AT42QT2161 50 History Initial release of document 9614A–AT42–08/10 ...

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... Notes 9614A–AT42–08/10 AT42QT2161 51 ...

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... LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’ ...