XC2VP100-6FF1704I Xilinx Inc, XC2VP100-6FF1704I Datasheet - Page 60

• Manufacturer Part Number: XC2VP100-6FF1704I
• Description: IC FPGA VIRTEX-II PRO 1704FFBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-II Pror

Specifications of XC2VP100-6FF1704I

• Number Of Logic Elements/cells: 99216
• Number Of Labs/clbs: 11024
• Total Ram Bits: 8183808
• Number Of I /o: 1040
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1704-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

DS083 (v4.7) November 5, 2007
Product Specification
Figure 55: Virtex-II Pro Clock Pads
R
Virtex-II Pro
Device
8 clock pads
8 clock pads
Figure 56: Virtex-II Pro Clock Multiplexer Buffer Configuration
DS083-2_42_052902
Clock
Pad
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Clock Distribution
Clock Multiplexer
www.xilinx.com
CLKOUT
CLKIN
DCM
Buffer
Clock
Clock
Pad
O
I
Each global clock multiplexer buffer can be driven either by
the clock pad to distribute a clock directly to the device, or
by the Digital Clock Manager (DCM), discussed in
Clock Manager (DCM), page
plexer buffer can also be driven by local interconnects. The
DCM has clock output(s) that can be connected to global
clock multiplexer buffer inputs, as shown in
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM+ blocks.
Eight global clocks can be used in each quadrant of the
Virtex-II Pro device. Designers should consider the clock
distribution detail of the device prior to pin-locking and floor-
planning. (See the Virtex-II Pro Platform FPGA User
Guide.)
Interconnect
DS083-2_43_122001
Local
51. Each global clock multi-
Figure
Module 2 of 4
56.
Digital
49