XC2V8000-5FF1517I Xilinx Inc, XC2V8000-5FF1517I Datasheet
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R DS031 (v3.5) November 5, 2007 Module 1: Introduction and Overview 7 pages • Summary of Features • General Description • Architecture • Device/Package Combinations and Maximum I/O • Ordering Examples Module 2: Functional Description 41 pages • Detailed ...
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R DS031-1 (v3.5) November 5, 2007 Summary of Virtex-II™ Features • Industry First Platform FPGA Solution • IP-Immersion Architecture - Densities from 40K to 8M system gates - 420 MHz internal clock speed (Advance Data) - 840+ Mb/s I/O ...
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... I/Os for each device and package using wire-bond or flip-chip technology. Table 2: Maximum Number of User I/O Pads Device XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 www.xilinx.com SelectRAM Blocks 18 Kbit Max RAM Max I/O Blocks (Kbits) DCMs Pads 144 ...
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R Architecture Virtex-II Array Overview Virtex-II devices are user-programmable gate arrays with various configurable elements. The Virtex-II architecture is optimized for high-density and high-performance logic designs. As shown in Figure 1, the programmable device is comprised of input/output blocks (IOBs) ...
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R • HSTL (Class I, II, III, and IV) • SSTL (3.3V and 2.5V, Class I and II) • AGP-2X The digitally controlled impedance (DCI) I/O feature auto- matically provides on-chip termination for each I/O element. The IOB elements also ...
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R Boundary Scan Boundary scan instructions and associated data registers support a standard methodology for accessing and config- uring Virtex-II devices that complies with IEEE standards 1149.1 — 1993 and 1532. A system mode and a test mode are implemented. ...
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R Table 6: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os (Advance Information) XC2V XC2V (1,2) Package 40 80 CS144/CSG144 88 92 FG256/FGG256 88 120 FG456/FGG456 - - FG676/FGG676 - - FF896 - - FF1152 - - FF1517 - ...
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R Revision History This section records the change history for this module of the data sheet. Date Version 11/07/00 1.0 Early access draft. 12/06/00 1.1 Initial release. 01/15/01 1.2 Added values to the tables in the Switching Characteristics 01/25/01 1.3 ...
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R DS031-2 (v3.5) November 5, 2007 Detailed Description Input/Output Blocks (IOBs) Virtex-II™ I/O blocks (IOBs) are provided in groups of two or four on the perimeter of each device. Each IOB can be used as input and/or output ...
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R Table 2: Supported Differential Signal I/O Standards Output Input I/O Standard V V CCO CCO (1) LVPECL_33 3.3 N/R LDT_25 2.5 N/R LVDS_33 3.3 N/R LVDS_25 2.5 N/R LVDSEXT_33 3.3 N/R LVDSEXT_25 2.5 N/R BLVDS_25 2.5 N/R ULVDS_25 2.5 ...
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CLOCK CLK1 D2 Q2 CLK2 (50/50 duty cycle clock) The DDR mechanism shown in Figure 3 ror a copy of the clock on the output. This is useful for prop- agating a clock along the data that ...
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R (O/T) 1 (O/T) CE (O/T) CLK1 SR Shared by all registers REV (O/T) CLK2 (O/T) 2 Figure 4: Register / Latch Configuration in an IOB Block V CCO Clamp OBUF Diode V CCO Program Current V CCO Program Delay ...
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R Table 4: LVTTL and LVCMOS Programmable Currents (Sink and Source) SelectI/O-Ultra LVTTL 2 mA LVCMOS33 2 mA LVCMOS25 2 mA LVCMOS18 2 mA LVCMOS15 2 mA Figure 6 shows the SSTL2, SSTL3, and HSTL configura- tions. HSTL can sink ...
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R Bank 0 Bank 1 Bank 5 Bank 4 Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond Packages (CS/CSG, FG/FGG, & BG/BGG) Some input standards require a user-supplied threshold voltage (V ), and certain user-I/O pins are automatically REF ...
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R Table 5: Summary of Voltage Supply Requirements for All Input and Output Standards V V CCO I/O Standard Output Input Input LVDS_33 N/R LVDSEXT_33 N/R LVPECL_33 N/R N/R SSTL3_I SSTL3_II AGP 1.32 LVTTL N/R LVCMOS33 3.3 N/R LVDCI_33 N/R ...
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R Digitally Controlled Impedance (DCI) Today’s chip output signals with fast edge rates require ter- mination to prevent reflections and maintain signal integrity. High pin count packages (especially ball grid arrays) can not accommodate external termination resistors. Virtex-II XCITE DCI ...
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R Table 8: SelectI/O-Ultra Differential Buffers With On-Chip Termination I/O Standard Description LVDS 2.5V LVDS Extended 2.5V Figure 11 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O standards. For a complete list, see the HSTL_I ...
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R Figure 12 provides examples illustrating the use of the SSTL2_I_DCI, SSTL2_II_DCI, SSTL3_I_DCI, and SSTL3_II_DCI I/O standards. For a complete list, see the SSTL2_I V /2 CCO R Conventional CCO DCI Transmit (1) 25Ω R ...
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R Figure 13 provides examples illustrating the use of the LVDS_DCI and LVDSEXT_DCI I/O standards. For a complete list, see the Virtex-II Platform FPGA User Conventional Conventional Transmit DCI Receive Reference Resistor Recommended Z 0 DS031-2 (v3.5) November 5, 2007 ...
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R Configurable Logic Blocks (CLBs) The Virtex-II configurable logic blocks (CLB) are organized in an array and are used to build combinatorial and synchro- nous logic designs. Each CLB element is tied to a switch matrix to access the general ...
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R SHIFTIN SOPIN WG4 WG3 WG2 WG1 ALTDIG BY SLICEWE[2:0] CE CLK SR DS031-2 (v3.5) November 5, 2007 Product Specification Virtex-II Platform FPGAs: Functional Description COUT 0 Dual-Port Shift-Reg MUXCY LUT A3 ...
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CLK SR BX Figure 17: Register / Latch Configuration in a Slice The set and reset functionality of a register or a latch can be configured as follows: • ...
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R Figure 18, Figure 19, and Figure 20 ple configurations. RAM 16x1S RAM 4 D A[3:0] A[4:1] 4 WG[4: (BY) D WSG (SR WCLK CK Figure 18: Distributed SelectRAM (RAM16x1S) RAM 32x1S (BX) A[4] RAM 4 ...
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R Shift Registers Each function generator can also be configured as a 16-bit shift register. The write operation is synchronous with a clock input (CLK) and an optional clock enable, as shown in Figure 21. A dynamic read access is ...
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R Multiplexers Virtex-II function generators and associated multiplexers can implement the following: • 4:1 multiplexer in one slice • 8:1 multiplexer in two slices • 16:1 multiplexer in one CLB element (4 slices) • 32:1 multiplexer in two CLB elements ...
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R COUT the next CLB (First Carry Chain LUT O I LUT CIN COUT O I LUT O I LUT CIN DS031-2 (v3.5) November 5, 2007 Product Specification Virtex-II Platform FPGAs: Functional Description LUT LUT ...
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R Sum of Products Each Virtex-II slice has a dedicated OR gate named ORCY, ORing together outputs from the slices carryout and the ORCY from an adjacent slice. The ORCY gate with the dedicated Sum of Products (SOP) chain are ...
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... Device Slice S3 XC2V40 XC2V80 Slice S2 XC2V250 XC2V500 XC2V1000 XC2V1500 DS031_37_060700 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 Programmable Switch connection matrix CLB-II Table 13 shows the available resources in all CLBs. Arithmetic & MULT_ANDs Carry-Chains 8 2 www.xilinx.com Figure 28. The switch matrices corresponding shows the number of 3-state buffers available in ...
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... XC2V3000 14,336 XC2V4000 23,040 XC2V6000 33,792 XC2V8000 112 x 104 46,592 Notes: 1. The carry-chains and SOP chains can be split or cascaded. 18 Kbit Block SelectRAM Resources Introduction Virtex-II devices incorporate large amounts of 18 Kbit block SelectRAM. These complement the distributed SelectRAM resources that provide shallow RAM structures imple- mented in CLBs ...
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R 18 Kbit Block SelectRAM DI DIP ADDR WE EN SSR CLK Figure 29: 18 Kbit Block SelectRAM Memory in Single-Port Mode Table 15: Dual-Port Mode Configurations Port A 16K x 1 Port B 16K x 1 Port A 8K ...
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R Each block SelectRAM cell is a fully synchronous memory, as illustrated in Figure 30. The two ports have independent inputs and outputs and are independently clocked. 18 Kbit Block SelectRAM DIA DIPA ADDRA WEA ENA SSRA CLKA DIB DIPB ...
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... CLBs in a column divided by four. Column loca- No change during write tions are shown in Table 18: SelectRAM Memory Floor Plan Device XC2V40 XC2V80 XC2V250 New XC2V500 XC2V1000 DS031_12_102000 XC2V1500 XC2V2000 XC2V3000 Table 17. All control XC2V4000 XC2V6000 XC2V8000 www.xilinx.com Table 18. SelectRAM Blocks Columns Per Column Total ...
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... DS031-2 (v3.5) November 5, 2007 Product Specification SelectRAM Blocks SelectRAM Blocks Table 19: Virtex-II SelectRAM Memory Available Device XC2V3000 XC2V4000 XC2V6000 in Bits XC2V8000 72 73,728 18-Bit x 18-Bit Multipliers 144 147,456 Introduction 432 442,368 A Virtex-II multiplier block is an 18-bit by 18-bit 2’s comple- 576 589,824 ment signed multiplier ...
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... Table 20: Multiplier Floor Plan Device XC2V40 XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 www.xilinx.com Figure 36 shows a multiplier block. Multiplier Block MULT DS031_40_100400 Figure 36: Multiplier Block Configurable Logic Blocks (CLBs)). Multipliers Columns Per Column Total ...
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R Multiplier Blocks Figure 37: Multipliers (2-column, 4-column, and 6-column) Global Clock Multiplexer Buffers Virtex-II devices have 16 clock input pins that can also be used as regular user I/Os. Eight clock pads are on the top edge of the ...
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R Clock Pad I Clock Buffer 0 Clock Distribution Figure 39: Virtex-II Clock Distribution Configurations NW 16 Clocks SW 8 BUFGMUX The most common configuration option of this element buffer. A BUFG function in this (global buffer) ...
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R BUFGCE I CE DS031_62_101200 Figure 42: Virtex-II BUFGCE Function If the CE input is inactive (Low) prior to the incoming rising clock edge, the following clock pulse does not pass through the clock buffer, and the output stays Low. ...
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R DCM CLKIN CLKFB RST DSSEN PSINCDEC PSEN PSCLK clock signal control signal Figure 45: Digital Clock Manager The DCM can be configured to delay the completion of the Virtex-II configuration process until after the DCM has achieved lock. This ...
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R CLKIN CLKOUT_PHASE_SHIFT = NONE CLKFB CLKIN CLKOUT_PHASE_SHIFT = FIXED CLKFB CLKIN CLKOUT_PHASE_SHIFT = VARIABLE CLKFB Table 22 lists fine-phase shifting control pins, when used in variable mode. Table 22: Fine-Phase Shifting Control Pins Control Pin Direction PSINCDEC in Increment ...
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... XC2V2000 4 XC2V3000 6 XC2V4000 6 XC2V6000 6 XC2V8000 6 Active Interconnect Technology Local and global Virtex-II routing resources are optimized for speed and timing predictability, as well as to facilitate IP cores implementation. Virtex-II Active Interconnect Technol- ogy is a fully buffered programmable routing matrix. All rout- Switch Switch ...
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R Place-and-route software takes advantage of this regular array to deliver optimum system performance and fast com- pile times. The segmented routing resources are essential to guarantee IP cores portability and to efficiently handle an incremental design flow that is ...
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R Creating a Design Creating Virtex-II designs is easy with Xilinx Integrated Syn- thesis Environment (ISE) development systems, which sup- port advanced design capabilities, including ProActive Timing Closure, integrated logic analysis, and the fastest place and route runtimes in the ...
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... By preserving the logic in unchanged portions of a design, Xilinx incremental design makes the high-density design process more efficient. Xilinx hierarchical floorplanning capabilities can be speci- ...
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R Configuration Virtex-II devices are configured by loading application spe- cific configuration data into the internal configuration mem- ory. Configuration is carried out using a subset of the device pins, some of which are dedicated, while others can be re-used ...
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... XC2V1500 5,170,208 XC2V2000 6,812,960 XC2V3000 10,494,368 XC2V4000 15,659,936 XC2V6000 21,849,504 XC2V8000 26,194,208 Configuration Sequence The configuration of Virtex-II devices is a three-phase pro- cess after Power On Reset or POR. POR occurs when V is greater than 1.2V, V CCINT CCAUX DS031-2 (v3.5) November 5, 2007 Product Specification IEEE 1532 standard for In-System Configurable (ISC) devices ...
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R ments to begin changing state in response to the logic and the user clock. The relative timing of these events can be changed via con- figuration options in software. In addition, the GTS and GWE events can be made ...
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R Date Version 07/16/02 2.0 • • 09/26/02 2.1 • 12/06/02 2.1.1 • • • 05/07/03 2.1.2 • • • 06/19/03 2.2 • 08/01/03 3.0 All Virtex-II devices and speed grades now Production. See Table 13, Module 3. 10/14/03 3.1 ...
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R Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ...
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R DS031-3 (v3.5) November 5, 2007 Virtex-II Electrical Characteristics Virtex-II™ devices are provided in -6, -5, and -4 speed grades, with -6 having the highest performance. Virtex-II DC and AC characteristics are specified for both commercial and industrial ...
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R Table 2: Recommended Operating Conditions Symbol Description V Internal supply voltage relative to GND CCINT V Auxiliary supply voltage relative to GND CCAUX V Supply voltage relative to GND CCO (1) V Battery voltage relative to GND BATT Notes: ...
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... XC2V500 XC2V1000 (1,2) XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 If any V CCO draws up to 300 mA, worst case, until the V (2) up. This does not harm the device. If the current is limited to the minimum value above, or larger, the device powers on properly after all three supplies have passed through their power-on reset threshold voltages ...
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... V – 0.4 8 CCO 0.4 V – 0.4 16 CCO 0.4 V – 0.4 24 CCO 0.4 V – 0.4 48 CCO XC2V8000 1100 100 100 , but only if CCO , “Man- with CCO – 24 – 24 – 24 – 16 – 16 Note 2 Note 2 Note 2 n/a n/a – 8 – 16 – 8 – ...
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R Table 6: DC Input and Output Levels (Continued) V Input/Output IL Standard V, Min V, Max SSTL3 I – 0.5 V REF SSTL3 II – 0.5 V REF SSTL2 I – 0.5 V REF SSTL2 II – 0.5 V ...
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R Extended LVDS DC Specifications (LVDSEXT_33 & LVDSEXT_25) Table 9: Extended LVDS DC Specifications DC Parameter Supply Voltage Output High voltage for Q and Q Output Low voltage for Q and Q Differential output voltage (Q – Q ...
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R Virtex-II Performance Characteristics This section provides the performance characteristics of some common functions and designs implemented in Virtex-II devices. The numbers reported here are worst-case values; they have all been fully characterized. Note that these values are subject to ...
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R Table 12: Register-to-Register Performance (Continued) Description 8-bit Adder 16-bit Adder 64-bit Adder 64-bit Counter 64-bit Accumulator Multiplier 18x18 (with Block RAM inputs) Multiplier 18x18 (with Register inputs) Memory Block RAM Single-Port 4096 x 4 bits Single-Port 2048 x 9 ...
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... XC2V4000 XC2V6000 XC2V8000 Symbol Device T All IOPI T XC2V40 IOPID XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 www.xilinx.com IOB Input Switching Characteristics 11. Speed Grade Designations Advance Preliminary Speed Grade - 0.69 0.76 0.88 1.92 2.11 2.43 1.92 2.11 2.43 1.92 2 ...
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... XC2V250 3.24/–2.04 XC2V500 3.24/–2.04 XC2V1000 3.24/–2.04 XC2V1500 3.24/–2.04 XC2V2000 3.24/–2.04 XC2V3000 3.33/–2.10 XC2V4000 3.33/–2.10 XC2V6000 3.61/–2.29 XC2V8000 T /T All IOICECK IOCKICE T All IOSRCKI T All IOSRIQ T All GSRQ Table www.xilinx.com Speed Grade ...
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R IOB Input Switching Characteristics Standard Adjustments Table 15 gives all standard-specific data input delay adjustments. Table 15: IOB Input Switching Characteristics Standard Adjustments Description LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS ), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V ...
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R Table 15: IOB Input Switching Characteristics Standard Adjustments (Continued) Description LVDCI, 3.3V, Half-Impedance LVDCI, 2.5V, Half-Impedance LVDCI, 1.8V, Half-Impedance LVDCI, 1.5V, Half-Impedance HSLVDCI (High-Speed Low-Voltage DCI), 1.5V HSLVDCI, 1.8V HSLVDCI, 2.5V HSLVDCI, 3.3V GTL (Gunning Transceiver Logic) with DCI ...
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R IOB Output Switching Characteristics Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust the delays with the values shown in Table 16: IOB Output Switching Characteristics ...
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R IOB Output Switching Characteristics Standard Adjustments Table 17 gives all standard-specific adjustments for output delays terminating at pads, based on standard capacitive load Output delays terminating at a pad are specified for LVTTL with 12 mA drive ...
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R Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued) Description LVCMOS, 2.5V, Fast LVCMOS, 2.5V, Fast LVCMOS, 1.8V, Slow LVCMOS, 1.8V, Slow LVCMOS, 1.8V, Slow LVCMOS, 1.8V, Slow, 8 ...
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R Table 17: IOB Output Switching Characteristics Standard Adjustments (Continued) Description HSTL, Class II, 1.8V HSTL, Class III, 1.8V HSTL, Class IV, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, ...
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R Standard Adjustment Measurement Methodology I/O Input Delay Measurements Table 18 shows the test setup parameters used for measuring Input standard adjustments (see Table 18: Input Delay Measurement Methodology Description LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V ...
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R Output Delay Measurements Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all test- ing. (See Virtex-II Platform FPGA User Guide The propagation ...
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R Table 19: Output Delay Measurement Methodology Description SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V SSTL, Class II, 2.5V SSTL, Class I, 3.3V SSTL, Class II, 3.3V AGP-2X/AGP (Accelerated Graphics Port) ...
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R Clock Distribution Switching Characteristics Table 20: Clock Distribution Switching Characteristics Description Global Clock Buffer I input to O output Global Clock Buffer S input Setup/Hold inputs CLB Switching Characteristics Delays originating at F/G inputs vary ...
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R CLB Distributed RAM Switching Characteristics Table 22: CLB Distributed RAM Switching Characteristics Description Sequential Delays Clock CLK to X/Y outputs (WE active mode Clock CLK to X/Y outputs (WE active mode ...
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R Multiplier Switching Characteristics Table 24: Multiplier Switching Characteristics Description Propagation Delay to Output Pin Input to Pin 35 Input to Pin 34 Input to Pin 33 Input to Pin 32 Input to Pin 31 Input to Pin 30 Input ...
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R Table 25: Pipelined Multiplier Switching Characteristics Description Setup and Hold Times Before/After Clock Data Inputs Clock Enable Reset Clock to Output Pin Clock to Pin 35 Clock to Pin 34 Clock to Pin 33 Clock to Pin 32 Clock ...
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R Enhanced Multiplier Switching Characteristics Table 26 and Table 27 provide timing information for enhanced Virtex-II multiplier blocks, available in stepping revisions of Virtex-II devices. For more information on stepping revisions, availability, and ordering instructions, see your local sales representative. ...
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R Table 27: Enhanced Pipelined Multiplier Switching Characteristics Description Setup and Hold Times Before/After Clock Data Inputs Clock Enable Reset Clock to Output Pin Clock to Pin 35 Clock to Pin 34 Clock to Pin 33 Clock to Pin 32 ...
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R Block SelectRAM Switching Characteristics Table 28: Block SelectRAM Switching Characteristics Description Sequential Delays Clock CLK to DOUT output Setup and Hold Times Before Clock CLK ADDR inputs DIN inputs EN input RST input WEN input Clock CLK CLKA to ...
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R Configuration Timing Configuration Memory Clearing Parameters Power-up timing of configuration signals is shown PROG_B INIT_B CCLK (Output or Input) M0, M1, M2* (Required) Table 30: Power-Up Timing Characteristics Description Power-on reset Program latency CCLK (output) delay ...
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R Serial DIN CCLK Serial DOUT CCLK (Output) 1 Serial DIN Serial DOUT . Table 31: Master/Slave Serial Mode Timing Characteristics Description DIN setup/hold, slave mode DIN setup/hold, master mode DOUT High time CCLK Low time Maximum start-up frequency Maximum ...
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R CCLK 3 T CS_B SMCSCC 5 T RDWR_B SMCCW T DATA[0:7] BUSY Figure 5: SelectMAP Mode Data Loading Sequence (Generic) Table 32: SelectMAP Mode Write Timing Characteristics Description DATA[0:7] setup/hold CS_B setup/hold RDWR_B setup/hold CCLK BUSY propagation delay Maximum ...
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R JTAG Test Access Port Switching Characteristics Characterization data for some of the most commonly requested timing parameters shown in FI TMS TDI TCK TDO Data to be captured Data to be driven out Figure 6: Virtex-II Pro Boundary Scan ...
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... DS031-3 (v3.5) November 5, 2007 Product Specification Virtex-II Platform FPGAs: DC and Switching Characteristics Symbol Device T XC2V40 ICKOFDCM XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 threshold with test setup shown in Figure CC www.xilinx.com Speed Grade - 1.10 1.28 1.48 1.10 1.28 1.48 1.10 1.28 1 ...
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... Product Specification Virtex-II Platform FPGAs: DC and Switching Characteristics Symbol Device 14. T XC2V40 ICKOF XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 threshold with test setup shown in Figure CC www.xilinx.com Speed Grade - 3.46 3.58 3.69 3.62 3.58 3.69 3.79 3.88 4.47 3 ...
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... Symbol Device T /T XC2V40 PSDCM PHDCM XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 www.xilinx.com Speed Grade - 1.60/–0.90 1.60/–0.90 1.84/–0.76 1.60/–0.90 1.60/–0.90 1.84/–0.76 1.60/–0.90 1.60/–0.90 1.84/–0.76 1.60/–0.90 1.60/–0.90 1.84/– ...
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... XC2V500 1.92/ 0.00 XC2V1000 1.92/ 0.00 XC2V1500 1.92/ 0.00 XC2V2000 1.92/ 0.00 XC2V3000 1.92/ 0.00 XC2V4000 2.00/ 0.00 XC2V6000 1.92/ 0.50 XC2V8000 www.xilinx.com Speed Grade - 1.92/ 0.00 2.21/ 0.00 2.10/ 0.00 2.21/ 0.00 1.92/ 0.00 2.21/ 0.00 1.92/ 0.00 2.21/ 0.00 1 ...
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R DCM Timing Parameters All devices are 100% functionally tested. Because of the dif- ficulty in directly measuring many internal timing parame- ters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values Operating Frequency Ranges ...
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R Input Clock Tolerances Table 39: Input Clock Tolerances Description Input Clock Low/High Pulse Width PSCLK PSCLK_PULSE PSCLK_PULSE and (3) PSCLK and CLKIN CLKIN_PULSE Input Clock Cycle-Cycle Jitter (Low Frequency Mode) (1) CLKIN (using DLL outputs) CLKIN_CYC_JITT_DLL_LF (2) CLKIN (using ...
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R Output Clock Jitter Table 40: Output Clock Jitter Description Clock Synthesis Period Jitter CLK0 CLK90 CLK180 CLK270 CLK2X, CLK2X180 CLKDV (integer division) CLKDV (non-integer division) CLKFX, CLKFX180 Notes: 1. Values for this parameter are available at www.xilinx.com. Output Clock ...
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R Miscellaneous Timing Parameters Table 42: Miscellaneous Timing Parameters Description Time Required to Achieve LOCK (1) Using DLL outputs LOCK_DLL LOCK_DLL_60 LOCK_DLL_50_60 LOCK_DLL_40_50 LOCK_DLL_30_40 LOCK_DLL_24_30 Using CLKFX outputs LOCK_FX_MIN LOCK_FX_MAX Additional lock time with LOCK_DLL_FINE_SHIFT fine-phase shifting Fine-Phase Shifting Absolute ...
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... Device T All DCD_CLK0 T All DCD_CLK180 T XC2V40 CKSKEW XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 Symbol Device/Package T XC2V1000 / FF896 PKGSKEW XC2V3000 / FF1152 XC2V3000 / BF957 XC2V4000 / FF1152 XC2V4000 / FF1517 XC2V4000 / BF957 XC2V6000 / FF1152 XC2V6000 / FF1517 XC2V6000 / BF957 www.xilinx.com Speed Grade - ...
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... XC2V6000 XC2V8000 DCD_CLK180 Symbol Device IOB Input Switching 11 XC2V40 PSDCM T PHDCM XC2V80 XC2V250 XC2V500 XC2V1000 XC2V1500 XC2V2000 XC2V3000 XC2V4000 XC2V6000 XC2V8000 www.xilinx.com Speed Grade - 500 500 550 500 500 550 500 500 550 500 500 550 500 500 550 500 500 ...
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R Source Synchronous Timing Budgets This section describes how to use the parameters provided in the develop system-specific timing budgets. The following analysis provides information necessary for determining Virtex-II contributions to an overall system timing analysis; no assumptions are made ...
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... JEDEC specification. PCI compliance to IN CLKOUT_DUTY_CYCLE_DLL Virtex-II Performance Characteristics tables, based on values extracted from speedsfile version 1.114. 4, Quiescent Supply Current, and Devices: Added parameters for XC2V8000 device. 16, IOB Output Switching Characteristics: Changed parameter designator IOTON IOTP 26, Enhanced Multiplier Switching ...
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... In section - - - - • Table now available in these tables. • XC2V8000 is no longer offered in the -6 speed grade. The following tables containing parameters or other references to this device/grade combination were corrected accordingly: Table • Table Footnote (2) to new Footnote (3). 03/29/04 3.2 • Table ...
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R Date Version 03/01/05 3.4 • Table (cont’d) (cont’d) include descriptions, as well as the actual IOSTANDARD attributes (used in Xilinx ISE™ software) for all I/O standards. • Table SSTL18_I_DCI, SSTL18_II_DCI, HSTL_I_18, HSTL_II_18, HSTL_III_18, HSTL_IV_18, LVDSEXT_25, LVDSEXT_33, BLVDS_25, LVDS_25_DCI, LVDS_33_DCI, ...
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R 6 DS031-4 (v3.5) November 5, 2007 This document provides Virtex-II™ Device/Package Combi- nations, Maximum I/Os Available, and Virtex-II Pin Defini- tions, followed by pinout tables for the following packages: • CS144/CSG144 Chip-Scale BGA Package • FG256/FGG256 Fine-Pitch ...
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R Table 3: Virtex-II Device/Package Combinations and Maximum Number of Available I/Os XC2V XC2V Package 40 80 CS144 88 92 FG256 88 120 FG456 - - FG676 - - FF896 - - FF1152 - - FF1517 - - BG575 - ...
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R Pin Definitions Table 4 provides a description of each pin type listed in Virtex-II pinout tables. Table 4: Virtex-II Pin Definitions Pin Name Direction User I/O Pins IO_LXXY_# Input/Output/ Bidirectional Dual-Function Pins IO_LXXY_#/ZZZ With /ZZZ: D0/DIN, D1, D2, Input/Output ...
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R Table 4: Virtex-II Pin Definitions (Continued) Pin Name Direction PROG_B Input DONE Input/Output M2, M1, M0 Input HSWAP_EN Input TCK Input TDI Input TDO Output TMS Input PWRDWN_B Input (unsupported) Other Pins DXN, DXP N/A V Input BATT RSVD ...
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R CS144/CSG144 Chip-Scale BGA Package As shown in Table 5, XC2V40, XC2V80, and XC2V250 Virtex-II devices are available in the CS144/CSG144 package. Pins in the XC2V40, XC2V80, and XC2V250 devices are the same except for pin differences in the XC2V40 ...
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R Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250 Bank Pin Description 2 IO_L96N_2 2 IO_L96P_2 3 IO_L96N_3 3 IO_L96P_3 3 IO_L94N_3 3 IO_L94P_3 3 IO_L03N_3/VREF_3 3 IO_L03P_3 3 IO_L02N_3/VRP_3 3 IO_L02P_3/VRN_3 3 IO_L01N_3 3 IO_L01P_3 4 IO_L01N_4/BUSY/DOUT 4 IO_L01P_4/INIT_B ...
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R Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250 Bank Pin Description 6 IO_L01P_6 6 IO_L01N_6 6 IO_L02P_6/VRN_6 6 IO_L02N_6/VRP_6 6 IO_L03P_6 6 IO_L03N_6/VREF_6 6 IO_L94P_6 6 IO_L94N_6 6 IO_L96P_6 6 IO_L96N_6 7 IO_L96P_7 7 IO_L96N_7 7 IO_L94P_7 7 IO_L94N_7 ...
Page 100
R Table 5: CS144/CSG144 — XC2V40, XC2V80, and XC2V250 Bank Pin Description NA CCLK NA PROG_B NA DONE TCK NA TDI NA TDO NA TMS NA PWRDWN_B NA HSWAP_EN NA RSVD NA RSVD ...
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R CS144/CSG144 Chip-Scale BGA Package Specifications (0.80mm pitch) Figure 1: CS144/CSG144 Chip-Scale BGA Package Specifications DS031-4 (v3.5) November 5, 2007 Product Specification Virtex-II Platform FPGAs: Pinout Information www.xilinx.com Module ...
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R FG256/FGG256 Fine-Pitch BGA Package As shown in Table 6, XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG256/FGG256 fine-pitch BGA package. The pins in the XC2V250, XC2V500, and XC2V1000 devices are same. The No Connect ...
Page 103
R Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description 1 IO_L92P_1 1 IO_L05N_1 1 IO_L05P_1 1 IO_L04N_1 1 IO_L04P_1/VREF_1 1 IO_L03N_1/VRP_1 1 IO_L03P_1/VRN_1 1 IO_L02N_1 1 IO_L02P_1 1 IO_L01N_1 1 IO_L01P_1 2 IO_L01N_2 2 ...
Page 104
R Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description 3 IO_L96N_3 3 IO_L96P_3 3 IO_L94N_3 3 IO_L94P_3 3 IO_L93N_3/VREF_3 3 IO_L93P_3 3 IO_L91N_3 3 IO_L91P_3 3 IO_L45N_3/VREF_3 3 IO_L45P_3 3 IO_L43N_3 3 IO_L43P_3 3 ...
Page 105
R Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description 4 IO_L91N_4/VREF_4 4 IO_L91P_4 4 IO_L92N_4 4 IO_L92P_4 4 IO_L93N_4 4 IO_L93P_4 4 IO_L94N_4/VREF_4 4 IO_L94P_4 4 IO_L95N_4/GCLK3S 4 IO_L95P_4/GCLK2P 4 IO_L96N_4/GCLK1S 4 IO_L96P_4/GCLK0P 5 ...
Page 106
R Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description 5 IO_L01P_5/CS_B 6 IO_L01P_6 6 IO_L01N_6 6 IO_L02P_6/VRN_6 6 IO_L02N_6/VRP_6 6 IO_L03P_6 6 IO_L03N_6/VREF_6 6 IO_L04P_6 6 IO_L04N_6 6 IO_L06P_6 6 IO_L06N_6 6 IO_L43P_6 6 ...
Page 107
R Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description 7 IO_L45N_7 7 IO_L43P_7 7 IO_L43N_7 7 IO_L06P_7 7 IO_L06N_7 7 IO_L04P_7 7 IO_L04N_7 7 IO_L03P_7/VREF_7 7 IO_L03N_7 7 IO_L02P_7/VRN_7 7 IO_L02N_7/VRP_7 7 IO_L01P_7 7 ...
Page 108
R Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description 6 VCCO_6 7 VCCO_7 7 VCCO_7 7 VCCO_7 NA CCLK NA PROG_B NA DONE HSWAP_EN NA TCK NA ...
Page 109
R Table 6: FG256/FGG256 BGA — XC2V40, XC2V80, XC2V250, XC2V500, and XC2V1000 Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 110
R FG256/FGG256 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 2: FG256/FGG256 Fine-Pitch BGA Package Specifications DS031-4 (v3.5) November 5, 2007 Product Specification Virtex-II Platform FPGAs: Pinout Information www.xilinx.com Module ...
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R FG456/FGG456 Fine-Pitch BGA Package As shown in Table 7, XC2V250, XC2V500, and XC2V1000 Virtex-II devices are available in the FG456/FGG456 fine-pitch BGA package. Pins in the XC2V250, XC2V500, and XC2V1000 devices are the same, except for the pin differences ...
Page 112
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 0 IO_L93N_0 0 IO_L93P_0 0 IO_L94N_0/VREF_0 0 IO_L94P_0 0 IO_L95N_0/GCLK7P 0 IO_L95P_0/GCLK6S 0 IO_L96N_0/GCLK5P 0 IO_L96P_0/GCLK4S 1 IO_L96N_1/GCLK3P 1 IO_L96P_1/GCLK2S 1 IO_L95N_1/GCLK1P 1 IO_L95P_1/GCLK0S 1 IO_L94N_1 1 ...
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R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 1 IO_L21P_1 1 IO_L06N_1 1 IO_L06P_1 1 IO_L05N_1 1 IO_L05P_1 1 IO_L04N_1 1 IO_L04P_1/VREF_1 1 IO_L03N_1/VRP_1 1 IO_L03P_1/VRN_1 1 IO_L02N_1 1 IO_L02P_1 1 IO_L01N_1 1 IO_L01P_1 2 ...
Page 114
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 2 IO_L45N_2 2 IO_L45P_2/VREF_2 2 IO_L46N_2 2 IO_L46P_2 2 IO_L48N_2 2 IO_L48P_2 2 IO_L49N_2 2 IO_L49P_2 2 IO_L51N_2 2 IO_L51P_2/VREF_2 2 IO_L52N_2 2 IO_L52P_2 2 IO_L54N_2 2 ...
Page 115
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 3 IO_L52P_3 3 IO_L51N_3/VREF_3 3 IO_L51P_3 3 IO_L49N_3 3 IO_L49P_3 3 IO_L48N_3 3 IO_L48P_3 3 IO_L46N_3 3 IO_L46P_3 3 IO_L45N_3/VREF_3 3 IO_L45P_3 3 IO_L43N_3 3 IO_L43P_3 3 ...
Page 116
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 4 IO_L02N_4/D0/DIN 4 IO_L02P_4/D1 4 IO_L03N_4/D2/ALT_VRP_4 4 IO_L03P_4/D3/ALT_VRN_4 4 IO_L04N_4/VREF_4 4 IO_L04P_4 4 IO_L05N_4/VRP_4 4 IO_L05P_4/VRN_4 4 IO_L06N_4 4 IO_L06P_4 4 IO_L19N_4 4 IO_L19P_4 4 IO_L21N_4 4 ...
Page 117
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 4 IO_L95N_4/GCLK3S 4 IO_L95P_4/GCLK2P 4 IO_L96N_4/GCLK1S 4 IO_L96P_4/GCLK0P 5 IO_L96N_5/GCLK7S 5 IO_L96P_5/GCLK6P 5 IO_L95N_5/GCLK5S 5 IO_L95P_5/GCLK4P 5 IO_L94N_5 5 IO_L94P_5/VREF_5 5 IO_L93N_5 5 IO_L93P_5 5 IO_L92N_5 5 ...
Page 118
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 5 IO_L06P_5 5 IO_L05N_5/VRP_5 5 IO_L05P_5/VRN_5 5 IO_L04N_5 5 IO_L04P_5/VREF_5 5 IO_L03N_5/D4/ALT_VRP_5 5 IO_L03P_5/D5/ALT_VRN_5 5 IO_L02N_5/D6 5 IO_L02P_5/D7 5 IO_L01N_5/RDWR_B 5 IO_L01P_5/CS_B 6 IO_L01P_6 6 IO_L01N_6 6 ...
Page 119
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 6 IO_L46P_6 6 IO_L46N_6 6 IO_L48P_6 6 IO_L48N_6 6 IO_L49P_6 6 IO_L49N_6 6 IO_L51P_6 6 IO_L51N_6/VREF_6 6 IO_L52P_6 6 IO_L52N_6 6 IO_L54P_6 6 IO_L54N_6 6 IO_L91P_6 6 ...
Page 120
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 7 IO_L51N_7 7 IO_L49P_7 7 IO_L49N_7 7 IO_L48P_7 7 IO_L48N_7 7 IO_L46P_7 7 IO_L46N_7 7 IO_L45P_7/VREF_7 7 IO_L45N_7 7 IO_L43P_7 7 IO_L43N_7 7 IO_L24P_7 7 IO_L24N_7 7 ...
Page 121
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 0 VCCO_0 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 VCCO_3 3 VCCO_3 3 ...
Page 122
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description 7 VCCO_7 7 VCCO_7 NA CCLK NA PROG_B NA DONE HSWAP_EN NA TCK NA TDI NA TDO NA TMS NA ...
Page 123
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA GND NA GND NA GND NA ...
Page 124
R Table 7: FG456/FGG456 BGA — XC2V250, XC2V500, and XC2V1000 Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 125
R FG456/FGG456 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 3: FG456/FGG456 Fine-Pitch BGA Package Specifications DS031-4 (v3.5) November 5, 2007 Product Specification Virtex-II Platform FPGAs: Pinout Information www.xilinx.com Module ...
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R FG676/FGG676 Fine-Pitch BGA Package As shown in Table 8, XC2V1500, XC2V2000, and XC2V3000 Virtex-II devices are available in the FG676/FGG676 fine-pitch BGA package. Pins in the XC2V1500, XC2V2000, and XC2V3000 devices are the same, except for the pin differences ...
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R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 0 IO_L67P_0 0 IO_L69N_0 0 IO_L69P_0/VREF_0 0 IO_L70N_0 0 IO_L70P_0 0 IO_L72N_0 0 IO_L72P_0 0 IO_L73N_0 0 IO_L73P_0 0 IO_L75N_0 0 IO_L75P_0/VREF_0 0 IO_L76N_0 0 IO_L76P_0 0 ...
Page 128
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 1 IO_L92P_1 1 IO_L91N_1 1 IO_L91P_1/VREF_1 1 IO_L78N_1 1 IO_L78P_1 1 IO_L76N_1 1 IO_L76P_1 1 IO_L75N_1/VREF_1 1 IO_L75P_1 1 IO_L73N_1 1 IO_L73P_1 1 IO_L72N_1 1 IO_L72P_1 1 ...
Page 129
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 1 IO_L19N_1 1 IO_L19P_1 1 IO_L06N_1 1 IO_L06P_1 1 IO_L05N_1 1 IO_L05P_1 1 IO_L04N_1 1 IO_L04P_1/VREF_1 1 IO_L03N_1/VRP_1 1 IO_L03P_1/VRN_1 1 IO_L02N_1 1 IO_L02P_1 1 IO_L01N_1 1 ...
Page 130
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 2 IO_L45N_2 2 IO_L45P_2/VREF_2 2 IO_L46N_2 2 IO_L46P_2 2 IO_L48N_2 2 IO_L48P_2 2 IO_L49N_2 2 IO_L49P_2 2 IO_L51N_2 2 IO_L51P_2/VREF_2 2 IO_L52N_2 2 IO_L52P_2 2 IO_L54N_2 2 ...
Page 131
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 2 IO_L96P_2 3 IO_L96N_3 3 IO_L96P_3 3 IO_L94N_3 3 IO_L94P_3 3 IO_L93N_3/VREF_3 3 IO_L93P_3 3 IO_L91N_3 3 IO_L91P_3 3 IO_L78N_3 3 IO_L78P_3 3 IO_L76N_3 3 IO_L76P_3 3 ...
Page 132
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 3 IO_L46P_3 3 IO_L45N_3/VREF_3 3 IO_L45P_3 3 IO_L43N_3 3 IO_L43P_3 3 IO_L25N_3 3 IO_L25P_3 3 IO_L24N_3 3 IO_L24P_3 3 IO_L22N_3 3 IO_L22P_3 3 IO_L21N_3/VREF_3 3 IO_L21P_3 3 ...
Page 133
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 4 IO_L06P_4 4 IO_L19N_4 4 IO_L19P_4 4 IO_L21N_4 4 IO_L21P_4/VREF_4 4 IO_L22N_4 4 IO_L22P_4 4 IO_L24N_4 4 IO_L24P_4 4 IO_L25N_4 4 IO_L25P_4 4 IO_L27N_4 4 IO_L27P_4/VREF_4 4 ...
Page 134
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 4 IO_L78N_4 4 IO_L78P_4 4 IO_L91N_4/VREF_4 4 IO_L91P_4 4 IO_L92N_4 4 IO_L92P_4 4 IO_L93N_4 4 IO_L93P_4 4 IO_L94N_4/VREF_4 4 IO_L94P_4 4 IO_L95N_4/GCLK3S 4 IO_L95P_4/GCLK2P 4 IO_L96N_4/GCLK1S 4 ...
Page 135
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 5 IO_L70N_5 5 IO_L70P_5 5 IO_L69N_5/VREF_5 5 IO_L69P_5 5 IO_L67N_5 5 IO_L67P_5 5 IO_L54N_5 5 IO_L54P_5 5 IO_L52N_5 5 IO_L52P_5 5 IO_L51N_5/VREF_5 5 IO_L51P_5 5 IO_L49N_5 5 ...
Page 136
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 5 IO_L02P_5/D7 5 IO_L01N_5/RDWR_B 5 IO_L01P_5/CS_B 6 IO_L01P_6 6 IO_L01N_6 6 IO_L02P_6/VRN_6 6 IO_L02N_6/VRP_6 6 IO_L03P_6 6 IO_L03N_6/VREF_6 6 IO_L04P_6 6 IO_L04N_6 6 IO_L06P_6 6 IO_L06N_6 6 ...
Page 137
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 6 IO_L52N_6 6 IO_L54P_6 6 IO_L54N_6 6 IO_L67P_6 6 IO_L67N_6 6 IO_L69P_6 6 IO_L69N_6/VREF_6 6 IO_L70P_6 6 IO_L70N_6 6 IO_L72P_6 6 IO_L72N_6 6 IO_L73P_6 6 IO_L73N_6 6 ...
Page 138
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 7 IO_L78N_7 7 IO_L76P_7 7 IO_L76N_7 7 IO_L75P_7/VREF_7 7 IO_L75N_7 7 IO_L73P_7 7 IO_L73N_7 7 IO_L72P_7 7 IO_L72N_7 7 IO_L70P_7 7 IO_L70N_7 7 IO_L69P_7/VREF_7 7 IO_L69N_7 7 ...
Page 139
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 7 IO_L21P_7/VREF_7 7 IO_L21N_7 7 IO_L19P_7 7 IO_L19N_7 7 IO_L06P_7 7 IO_L06N_7 7 IO_L04P_7 7 IO_L04N_7 7 IO_L03P_7/VREF_7 7 IO_L03N_7 7 IO_L02P_7/VRN_7 7 IO_L02N_7/VRP_7 7 IO_L01P_7 7 ...
Page 140
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 4 VCCO_4 5 ...
Page 141
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description NA DONE HSWAP_EN NA TCK NA TDI NA TDO NA TMS NA PWRDWN_B NA DXN NA DXP NA VBATT NA ...
Page 142
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description NA VCCINT NA VCCINT NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 143
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 144
R Table 8: FG676/FGG676 BGA — XC2V1500, XC2V2000, and XC2V3000 Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 145
R FG676/FGG676 Fine-Pitch BGA Package Specifications (1.00mm pitch) Figure 4: FG676/FGG676 Fine-Pitch BGA Package Specifications DS031-4 (v3.5) November 5, 2007 Product Specification Virtex-II Platform FPGAs: Pinout Information www.xilinx.com Module ...
Page 146
R BG575/BGG575 Standard BGA Package As shown in Table 9, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the BG575/BGG575 BGA package. Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the pin differences in ...
Page 147
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 0 IO_L69P_0/VREF_0 0 IO_L70N_0 0 IO_L70P_0 0 IO_L72N_0 0 IO_L72P_0 0 IO_L73N_0 0 IO_L73P_0 0 IO_L91N_0/VREF_0 0 IO_L91P_0 0 IO_L92N_0 0 IO_L92P_0 0 IO_L93N_0 0 IO_L93P_0 0 ...
Page 148
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 1 IO_L70N_1 1 IO_L70P_1 1 IO_L69N_1/VREF_1 1 IO_L69P_1 1 IO_L67N_1 1 IO_L67P_1 1 IO_L54N_1 1 IO_L54P_1 1 IO_L52N_1 1 IO_L52P_1 1 IO_L51N_1/VREF_1 1 IO_L51P_1 1 IO_L49N_1 1 ...
Page 149
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 2 IO_L01P_2 2 IO_L02N_2/VRP_2 2 IO_L02P_2/VRN_2 2 IO_L03N_2 2 IO_L03P_2/VREF_2 2 IO_L04N_2 2 IO_L04P_2 2 IO_L06N_2 2 IO_L06P_2 2 IO_L19N_2 2 IO_L19P_2 2 IO_L21N_2 2 IO_L21P_2/VREF_2 2 ...
Page 150
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 2 IO_L69P_2/VREF_2 2 IO_L70N_2 2 IO_L70P_2 2 IO_L72N_2 2 IO_L72P_2 2 IO_L73N_2 2 IO_L73P_2 2 IO_L91N_2 2 IO_L91P_2 2 IO_L93N_2 2 IO_L93P_2/VREF_2 2 IO_L94N_2 2 IO_L94P_2 2 ...
Page 151
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 3 IO_L52N_3 3 IO_L52P_3 3 IO_L51N_3/VREF_3 3 IO_L51P_3 3 IO_L49N_3 3 IO_L49P_3 3 IO_L48N_3 3 IO_L48P_3 3 IO_L46N_3 3 IO_L46P_3 3 IO_L45N_3/VREF_3 3 IO_L45P_3 3 IO_L43N_3 3 ...
Page 152
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 4 IO_L02P_4/D1 4 IO_L03N_4/D2/ALT_VRP_4 4 IO_L03P_4/D3/ALT_VRN_4 4 IO_L04N_4/VREF_4 4 IO_L04P_4 4 IO_L05N_4/VRP_4 4 IO_L05P_4/VRN_4 4 IO_L06N_4 4 IO_L06P_4 4 IO_L19N_4 4 IO_L19P_4 4 IO_L21N_4 4 IO_L21P_4/VREF_4 4 ...
Page 153
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 4 IO_L91P_4 4 IO_L92N_4 4 IO_L92P_4 4 IO_L93N_4 4 IO_L93P_4 4 IO_L94N_4/VREF_4 4 IO_L94P_4 4 IO_L95N_4/GCLK3S 4 IO_L95P_4/GCLK2P 4 IO_L96N_4/GCLK1S 4 IO_L96P_4/GCLK0P 5 IO_L96N_5/GCLK7S 5 IO_L96P_5/GCLK6P 5 ...
Page 154
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 5 IO_L52N_5 5 IO_L52P_5 5 IO_L51N_5/VREF_5 5 IO_L51P_5 5 IO_L49N_5 5 IO_L49P_5 5 IO_L24N_5 5 IO_L24P_5 5 IO_L22N_5 5 IO_L22P_5 5 IO_L21N_5/VREF_5 5 IO_L21P_5 5 IO_L19N_5 5 ...
Page 155
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 6 IO_L06N_6 6 IO_L19P_6 6 IO_L19N_6 6 IO_L21P_6 6 IO_L21N_6/VREF_6 6 IO_L22P_6 6 IO_L22N_6 6 IO_L24P_6 6 IO_L24N_6 6 IO_L43P_6 6 IO_L43N_6 6 IO_L45P_6 6 IO_L45N_6/VREF_6 6 ...
Page 156
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 6 IO_L91N_6 6 IO_L93P_6 6 IO_L93N_6/VREF_6 6 IO_L94P_6 6 IO_L94N_6 6 IO_L96P_6 6 IO_L96N_6 7 IO_L96P_7 7 IO_L96N_7 7 IO_L94P_7 7 IO_L94N_7 7 IO_L93P_7/VREF_7 7 IO_L93N_7 7 ...
Page 157
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 7 IO_L46P_7 7 IO_L46N_7 7 IO_L45P_7/VREF_7 7 IO_L45N_7 7 IO_L43P_7 7 IO_L43N_7 7 IO_L24P_7 7 IO_L24N_7 7 IO_L22P_7 7 IO_L22N_7 7 IO_L21P_7/VREF_7 7 IO_L21N_7 7 IO_L19P_7 7 ...
Page 158
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 1 VCCO_1 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 4 ...
Page 159
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 7 VCCO_7 NA CCLK NA PROG_B NA DONE HSWAP_EN NA TCK NA TDI NA TDO NA TMS NA PWRDWN_B NA ...
Page 160
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA VCCINT NA ...
Page 161
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 162
R Table 9: BG575/BGG575 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA GND NA ...
Page 163
R BG575/BGG575 Standard BGA Package Specifications (1.27mm pitch) Figure 5: BG575/BGG575 Standard BGA Package Specifications DS031-4 (v3.5) November 5, 2007 Product Specification Virtex-II Platform FPGAs: Pinout Information www.xilinx.com Module ...
Page 164
R BG728/BGG728 Standard BGA Package As shown in Table 10, XC2V3000 Virtex-II devices are available in the BG728/BGG728 BGA package. Following this table are the BG728/BGG728 Standard BGA Package Specifications (1.27mm Table 10: BG728 BGA — XC2V3000 Bank 0 0 ...
Page 165
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 166
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 167
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 168
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 169
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 170
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 171
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 172
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 173
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 174
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 175
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 176
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 177
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 178
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 179
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 180
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 181
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 182
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 183
R Table 10: BG728 BGA — XC2V3000 Bank ...
Page 184
R Table 10: BG728 BGA — XC2V3000 Bank Notes: 1. See Table 4 for an explanation of the signals ...
Page 185
R BG728/BGG728 Standard BGA Package Specifications (1.27mm pitch) Figure 6: BG728/BGG728 Standard BGA Package Specifications DS031-4 (v3.5) November 5, 2007 Product Specification Virtex-II Platform FPGAs: Pinout Information www.xilinx.com Module ...
Page 186
R FF896 Flip-Chip Fine-Pitch BGA Package As shown in Table 11, XC2V1000, XC2V1500, and XC2V2000 Virtex-II devices are available in the FF896 flip-chip fine-pitch BGA package. Pins in the XC2V1000, XC2V1500, and XC2V2000 devices are the same, except for the ...
Page 187
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 0 IO_L53N_0 0 IO_L53P_0 0 IO_L54N_0 0 IO_L54P_0 0 IO_L67N_0 0 IO_L67P_0 0 IO_L68N_0 0 IO_L68P_0 0 IO_L69N_0 0 IO_L69P_0/VREF_0 0 IO_L70N_0 0 IO_L70P_0 0 IO_L71N_0 0 ...
Page 188
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 0 IO_L95P_0/GCLK6S 0 IO_L96N_0/GCLK5P 0 IO_L96P_0/GCLK4S 1 IO_L96N_1/GCLK3P 1 IO_L96P_1/GCLK2S 1 IO_L95N_1/GCLK1P 1 IO_L95P_1/GCLK0S 1 IO_L94N_1 1 IO_L94P_1/VREF_1 1 IO_L93N_1 1 IO_L93P_1 1 IO_L92N_1 1 IO_L92P_1 1 ...
Page 189
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 1 IO_L68P_1 1 IO_L67N_1 1 IO_L67P_1 1 IO_L54N_1 1 IO_L54P_1 1 IO_L53N_1 1 IO_L53P_1 1 IO_L52N_1 1 IO_L52P_1 1 IO_L51N_1/VREF_1 1 IO_L51P_1 1 IO_L50N_1 1 IO_L50P_1 1 ...
Page 190
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 1 IO_L01N_1 1 IO_L01P_1 2 IO_L01N_2 2 IO_L01P_2 2 IO_L02N_2/VRP_2 2 IO_L02P_2/VRN_2 2 IO_L03N_2 2 IO_L03P_2/VREF_2 2 IO_L04N_2 2 IO_L04P_2 2 IO_L05N_2 2 IO_L05P_2 2 IO_L06N_2 2 ...
Page 191
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 2 IO_L48N_2 2 IO_L48P_2 2 IO_L49N_2 2 IO_L49P_2 2 IO_L50N_2 2 IO_L50P_2 2 IO_L51N_2 2 IO_L51P_2/VREF_2 2 IO_L52N_2 2 IO_L52P_2 2 IO_L53N_2 2 IO_L53P_2 2 IO_L54N_2 2 ...
Page 192
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 2 IO_L78P_2 2 IO_L91N_2 2 IO_L91P_2 2 IO_L92N_2 2 IO_L92P_2 2 IO_L93N_2 2 IO_L93P_2/VREF_2 2 IO_L94N_2 2 IO_L94P_2 2 IO_L95N_2 2 IO_L95P_2 2 IO_L96N_2 2 IO_L96P_2 3 ...
Page 193
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 3 IO_L73P_3 3 IO_L72N_3 3 IO_L72P_3 3 IO_L71N_3 3 IO_L71P_3 3 IO_L70N_3 3 IO_L70P_3 3 IO_L69N_3/VREF_3 3 IO_L69P_3 3 IO_L68N_3 3 IO_L68P_3 3 IO_L67N_3 3 IO_L67P_3 3 ...
Page 194
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 3 IO_L24N_3 3 IO_L24P_3 3 IO_L23N_3 3 IO_L23P_3 3 IO_L22N_3 3 IO_L22P_3 3 IO_L21N_3/VREF_3 3 IO_L21P_3 3 IO_L20N_3 3 IO_L20P_3 3 IO_L19N_3 3 IO_L19P_3 3 IO_L06N_3 3 ...
Page 195
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 4 IO_L19N_4 4 IO_L19P_4 4 IO_L20N_4 4 IO_L20P_4 4 IO_L21N_4 4 IO_L21P_4/VREF_4 4 IO_L22N_4 4 IO_L22P_4 4 IO_L23N_4 4 IO_L23P_4 4 IO_L24N_4 4 IO_L24P_4 4 IO_L49N_4 4 ...
Page 196
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 4 IO_L73P_4 4 IO_L74N_4 4 IO_L74P_4 4 IO_L75N_4 4 IO_L75P_4/VREF_4 4 IO_L76N_4 4 IO_L76P_4 4 IO_L77N_4 4 IO_L77P_4 4 IO_L78N_4 4 IO_L78P_4 4 IO_L91N_4/VREF_4 4 IO_L91P_4 4 ...
Page 197
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 5 IO_L78P_5 5 IO_L77N_5 5 IO_L77P_5 5 IO_L76N_5 5 IO_L76P_5 5 IO_L75N_5/VREF_5 5 IO_L75P_5 5 IO_L74N_5 5 IO_L74P_5 5 IO_L73N_5 5 IO_L73P_5 5 IO_L72N_5 5 IO_L72P_5 5 ...
Page 198
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 5 IO_L23N_5 5 IO_L23P_5 5 IO_L22N_5 5 IO_L22P_5 5 IO_L21N_5/VREF_5 5 IO_L21P_5 5 IO_L20N_5 5 IO_L20P_5 5 IO_L19N_5 5 IO_L19P_5 5 IO_L06N_5 5 IO_L06P_5 5 IO_L05N_5/VRP_5 5 ...
Page 199
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 6 IO_L20P_6 6 IO_L20N_6 6 IO_L21P_6 6 IO_L21N_6/VREF_6 6 IO_L22P_6 6 IO_L22N_6 6 IO_L23P_6 6 IO_L23N_6 6 IO_L24P_6 6 IO_L24N_6 6 IO_L43P_6 6 IO_L43N_6 6 IO_L44P_6 6 ...
Page 200
R Table 11: FF896 BGA — XC2V1000, XC2V1500, and XC2V2000 Bank Pin Description 6 IO_L68N_6 6 IO_L69P_6 6 IO_L69N_6/VREF_6 6 IO_L70P_6 6 IO_L70N_6 6 IO_L71P_6 6 IO_L71N_6 6 IO_L72P_6 6 IO_L72N_6 6 IO_L73P_6 6 IO_L73N_6 6 IO_L74P_6 6 IO_L74N_6 6 ...