SST89V58RD2-33-C-NJE Microchip Technology, SST89V58RD2-33-C-NJE Datasheet
SST89V58RD2-33-C-NJE
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SST89V58RD2-33-C-NJE Summary of contents
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... Full-Duplex, Enhanced UART – Framing Error Detection – Automatic Address Recognition PRODUCT DESCRIPTION The SST89V54RD2/RD and SST89V58RD2/RD are members of the FlashFlex family of 8-bit microcontroller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS semiconductor pro- cess technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability bene- fits for SST’ ...
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... Full-Duplex, Enhanced UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.2 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.0 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.0 PROGRAMMABLE COUNTER ARRAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.1 PCA Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.2 PCA Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.3 Compare/Capture Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 Hard Lock ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD 2 FlashFlex MCU S71255-10-000 12/07 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 9.2 SoftLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.3 Security Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.4 Read Operation Under Lock Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2 Software Reset 10.3 Brown-out Detection Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.0 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11.1 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.0 POWER-SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12 ...
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... FIGURE 14-12: I Test Condition, Power-down Mode FIGURE 16-1: 40-pin Plastic Dual In-line Pins (PDIP FIGURE 16-2: 44-lead Plastic Lead Chip Carrier (PLCC FIGURE 16-3: 44-lead Thin Quad Flat Pack (TQFP ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD 4 FlashFlex MCU S71255-10-000 12/07 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD LIST OF TABLES TABLE 2-1: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TABLE 3-1: SFCF Values for Program Memory Block Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 TABLE 3-2: SFCF Values Under Different Reset Conditions TABLE 3-3: External Data Memory RD#, WR# with EXTRAM bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 TABLE 3-4: FlashFlex SFR Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 3-5: CPU related SFRs ...
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... Block 16K/32K x8 Secondary Block 8K x8 Timer 0 (16-bit) Timer 1 (16-bit) Timer 2 (16-bit) FIGURE 1-1: Functional Block Diagram ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD 8051 CPU Core ALU, ACC, B-Register, Instruction Register, Program Counter, Timing and Control Flash Control Unit RAM 1K x8 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 2.0 PIN ASSIGNMENTS (T2) P1.0 1 (T2 EX) P1.1 2 (ECI) P1.2 3 (CEX0) P1.3 4 (CEX1 / SS#) P1.4 5 (CEX2 / MOSI) P1.5 6 (CEX3 / MISO) P1.6 7 40-pin PDIP (CEX4 / SCK) P1.7 8 Top View RST 9 (RXD) P3.0 10 (TXD) P3.1 11 (INT0#) P3.2 12 (INT1#) P3.3 13 (T0) P3.4 14 (T1) P3.5 15 (WR#) P3 ...
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... RXD: Universal Asynchronous Receiver/Transmitter (UART) - Receive input P3[1] O TXD: UART - Transmit output ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD Port 0 also receives the code bytes during the external host mode OH. . Port 2 also receives some control signals and high-order address bits during the exter- 8 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD TABLE 2-1: Pin Descriptions (Continued Symbol Type Name and Functions P3[2] I INT0#: External Interrupt 0 Input P3[3] I INT1#: External Interrupt 1 Input P3[4] I T0: External count input to Timer/Counter 0 P3[5] I T1: External count input to Timer/Counter 1 P3[6] O WR#: External Data Memory Write strobe ...
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... FIGURE 3-1: Program Memory Organization for 16 KByte SST89x54RDx ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD bank selection. Please refer to Figures 3-1 and 3-2 for the program memory configuration. Program bank selection is described in the next section. The 16K/32K x8 primary SuperFlash block is organized as 128/256 sectors, each sector consists of 128 Bytes ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD EA FFFFH External 64 KByte 0000H FIGURE 3-2: Program Memory Organization for 32 KByte SST89x58RDx 3.2 Program Memory Block Switching The program memory block switching feature of the device allows either Block 1 or the lowest 8 KByte of Block used for the lowest 8 KByte of the program address space. SFCF[1:0] controls program memory block switching. ...
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... SFRs space are physically separate even though they have the same addresses. ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD When instructions access addresses in the upper 128 bytes (above 7FH), the MCU determines whether to access the SFRs or RAM by the type of instruction given indirect, then RAM is accessed ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD read and write signals (P3.6 - WR# and P3.7 - RD#) for external memory use. Table 3-3 shows external data mem- ory RD#, WR# operation with EXTRAM bit. TABLE 3-3: External Data Memory RD#, WR# with EXTRAM bit MOVX @DPTR MOVX A, @DPTR AUXR ADDR < ...
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... RAM 768 Bytes (Indirect Addressing) 000H 2FFH Expanded RAM 000H FIGURE 3-3: Internal and External Data Memory Structure ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD FFH FFH (Indirect Addressing) Upper 128 Bytes Internal RAM 80H 80H 7FH Lower 128 Bytes Internal RAM (Indirect & ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 3.5 Dual Data Pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1. (See Figure 3-4) ...
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... Power Control 8EH AUXR Auxiliary Reg A2H AUXR1 Auxiliary Reg 1 AEH 2 XICON External Interrupt Control 1. Bit Addressable SFRs Don’t care ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD Bit Address, Symbol, or Alternative Port Function MSB ACC[7:0] B[7: RS1 RS0 SP[7:0] DPL[7:0] DPH[7: ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD TABLE 3-6: Flash Memory Programming SFRs Direct Symbol Description Address B1H SFCF SuperFlash Configuration B2H SFCM SuperFlash Command B3H SFAL SuperFlash Address Low B4H SFAH SuperFlash Address High B5H SFDT SuperFlash Data B6H SFST SuperFlash Status TABLE ...
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... A0H 1 P2 Port 2 B0H 1 P3 Port 3 A5H 2 P4 Port 4 1. Bit Addressable SFRs similar to P1 and P3 ports ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD Bit Address, Symbol, or Alternative Port Function MSB Timer 1 GATE C/ GATE TF1 TR1 TF0 TR0 IE1 TH0[7:0] TL0[7:0] ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD TABLE 3-10: PCA SFRs Direct Symbol Description Address PCA Timer/Counter F9H CH E9H CL PCA Timer/Counter D8H 1 CCON Control Register PCA Timer/Counter D9H CMOD Mode Register FAH CCAP0H PCA Module 0 Compare/Capture EAH CCAP0L Registers FBH CCAP1H PCA Module 1 Compare/Capture ...
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... Mailbox register for interfacing with flash memory block. (Low order address register). SuperFlash Address Registers (SFAH) Location 7 6 B4H Symbol Function SFAH Mailbox register for interfacing with flash memory block. (High order address register). ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ FCM5 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD SuperFlash Data Register (SFDT) Location 7 6 B5H Symbol Function SFDT Mailbox register for interfacing with flash memory block. (Data register). SuperFlash Status Register (SFST) (Read Only Register) Location 7 6 B6H SB1_i SB2_i Symbol Function SB1 Security Bit 1 status (inverse of SB1 bit) ...
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... External 1 Interrupt Enable. ET0 Timer 0 Interrupt Enable. EX0 External 0 Interrupt Enable. Interrupt Enable A (IEA) Location 7 6 E8H - - Symbol Function EBO Brown-out Interrupt Enable Enable the interrupt 0 = Disable the interrupt ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ ET2 ES ET1 EX1 EBO 22 FlashFlex MCU ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD Interrupt Priority (IP) Location 7 6 B8H - PPC Symbol Function PPC PCA interrupt priority bit PT2 Timer 2 interrupt priority bit PS Serial Port interrupt priority bit PT1 Timer 1 interrupt priority bit PX1 External interrupt 1 priority bit PT0 Timer 0 interrupt priority bit ...
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... Flag survives if chip reset happened because of watchdog timer overflow. 1: Hardware sets the flag on watchdog overflow. WDT Watchdog timer refresh. 0: Hardware resets the bit when refresh is done. 1: Software sets the bit to force a watchdog timer refresh. SWDT Start watchdog timer. 0: Stop WDT. 1: Start WDT. ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD Watchdog Timer Data/Reload Register (WDTD) Location 7 6 85H Symbol Function WDTD Initial/Reload value in Watchdog Timer. New value won’t be effective until WDT is set. PCA Timer/Counter Control Register Location 7 6 D8H Bit addressable Symbol Function CF PCA Counter Overflow Flag Set by hardware when the counter rolls over ...
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... PCA Count Pulse Select bit 1 CPS0 PCA Count Pulse Select bit 2 CPS1 CPS0 OSC ECF PCA Enable Counter Overflow interrupt: 0: Disables the CF bit in CCON 1: Enables CF bit in CCON to generate an interrupt ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD 1 (CMOD CPS1 Selected 1 PCA Input 0 0 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD PCA Compare/Capture Module Mode Register Location 7 6 DAH - ECOM0 DBH - ECOM1 DCH - ECOM2 DDH - ECOM3 DEH - ECOM4 1. Not bit addressable Symbol Function - Not implemented, reserved for future use. Note: User should not write ‘1’s to reserved bits. The value read from a reserved bit is indeterminate. ...
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... Upon completion of data transfer, this bit is set SPIE =1 and ES =1, an interrupt is then generated. This bit is cleared by software. WCOL Write Collision Flag. Set if the SPI data register is written to during data transfer. This bit is cleared by software. ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ DORD MSTR CPOL CPHA ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD SPI Data Register (SPDR) Location 7 6 86H Power Control Register (PCON) Location 7 6 87H SMOD1 SMOD0 Symbol Function SMOD1 Double Baud rate bit. If SMOD1 = 1, Timer 1 is used to generate the baud rate, and the serial port is used in modes 1, 2, and 3. ...
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... RI Receive interrupt flag. Set by hardware at the end of the8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ SM2 REN ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD Timer/Counter 2 Control Register (T2CON) Location 7 6 C8H TF2 EXF2 Symbol Function TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1 ...
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... EX3 External Interrupt 3 Enable bit if set IE3 Interrupt Enable If IT3=1, IE3 is set/cleared automatically by hardware when interrupt is detected/ serviced. IT3 External Interrupt3 is falling-edge/low-level triggered when this bit is cleared by software. ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ IE3 IT3 0 EX2 32 FlashFlex MCU 2 1 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 4.0 FLASH MEMORY PROGRAMMING The device internal flash memory can be programmed or erased using the In-Application Programming (IAP) mode. 4.1 Product Identification The Read-ID command accesses the Signature Bytes that identify the device and the manufacturer as SST. External programmers primarily use these Signature Bytes in the selection of programming algorithms ...
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... SST89x5xRD2/RD, if SFAH[7] = 0b, the primary flash memory Block 0 is selected. If SFAH[7:4] = EH, the sec- ondary flash memory Block 1 is selected. The Block-Erase command sequence for SST89x5xRD2/ follows: ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD Erase Block 0 MOV SFAH, #00H Polling scheme MOV SFCM, #0DH ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 4.2.4.4 Byte-Program The Byte-Program command programs data into a single byte. The address is determined by the contents of SFAH and SFAL. The data byte is in SFDT. IAP Enable ORL SFCF, #40H Program byte address MOV SFAH, #byte_addressH MOV SFAL, #byte_addressL ...
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... Enable-Clock-Double command is used to make the MCU run at 6 clocks per machine cycle. The standard (default clocks per machine cycle (i.e. clock double command disabled). ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD Program Enable-Clock-Double Polling scheme MOV SFCM, #08H Polling SFST[2] indicates completion FIGURE 4 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 1 TABLE 4-2: IAP Commands Operation SFCM [6:0] 3 Chip-Erase Block-Erase Sector-Erase Byte-Program 8 Byte-Verify (Read) 9 Prog-SB1 9 Prog-SB2 9 Prog-SB3 9 Prog-SC0 9 Prog-SC1 9 Enable-Clock-Double 1. SFCF[6]=1 enables IAP commands; SFCF[6]=0 disables IAP commands. 2. Interrupt/Polling enable for flash operation completion SFCM[ Interrupt enable for flash operation completion 0: polling enable for flash operation completion 3 ...
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... Capture/Reload occurs on timer/counter overflow and transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generating mode. ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD 5.3 Programmable Clock-Out TMOD A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 6.0 SERIAL I/O 6.1 Full-Duplex, Enhanced UART The device serial I/O port is a full-duplex port that allows data to be transmitted and received simultaneously in hardware by the transmit and receive registers, respec- tively, while the software is performing other tasks. The transmit and receive registers are both located in the Serial Data Buffer (SBUF) special function register ...
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... Data Sheet RXD Start bit RI SMOD0=X FE SMOD0=1 FIGURE 6-2: UART Timings in Mode 1 RXD Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 FIGURE 6-3: UART Timings in Modes 2 and 3 ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ Data byte Data byte 40 FlashFlex MCU D6 D7 Stop bit 1255 F17.0 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 6.1.2 Automatic Address Recognition Automatic Address Recognition helps to reduce the MCU time and power required to talk to multiple serial devices. Each device is hooked together sharing the same serial link with its own address. In this configuration, a device is only interrupted when it receives its own address, thus eliminating the software overhead to compare addresses ...
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... MSB Master LSB SPI Clock Generator FIGURE 6-4: SPI Master-slave Interconnection ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD 6.2 Serial Peripheral Interface 6.2.1 SPI Features • Master or slave operation • 10 MHz bit frequency (max) • ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 6.2.3 SPI Transfer Formats SCK Cycle # 1 (for reference) SCK (CPOL=0) SCK (CPOL=1) MOSI MSB (from Master) MISO MSB (from Slave) SS# (to Slave) FIGURE 6-5: SPI Transfer Format with CPHA = 0 SCK Cycle # 1 (for reference) SCK (CPOL=0) SCK (CPOL=1) ...
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... WDTC FIGURE 7-1: Block Diagram of Programmable Watchdog Timer ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD The WDTS flag bit is set by WDT overflow and is not changed by WDT reset. User software can clear WDTS by writing “1” to it. Figure 7-1 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control watchdog timer operation ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 8.0 PROGRAMMABLE COUNTER ARRAY The Programmable Counter Array (PCA) present on the SST89V5xRD2/ special 16-bit timer that has five 16-bit capture/compare modules. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed out- put, or pulse width modulator ...
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... CCF4 for module 4, etc.). They are set when either a match or capture occurs. These flags can only be cleared by software. (See “PCA Timer/Counter Control Register (CCON)” on page 25.) ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD Clock Increments 12 MHz 1 µsec 330 nsec 256 µ ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 8.3 Compare/Capture Modules Each PCA module has an associated SFR with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. Refer to “PCA Compare/Capture Module Mode Reg- ister (CCAPMn)” on page 27 for details. The registers each contain 7 bits which are used to control the mode each module will operate in ...
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... A 0 disables toggle function enables toggle function on CEX[4:0] pin. 5. Enabling an interrupt for the Watchdog Timer would defeat the purpose of the Watchdog Timer. 6. For PCA WDT mode, also set the WDTE bit in the CMOD register to enable the reset output signal. ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 8.3.1 Capture Mode Capture mode is used to capture the PCA timer/counter value into a module’s capture registers (CCAPnH and CCAPnL). The capture will occur on a positive edge, nega- tive edge, or both on the corresponding module’s pin. To use one of the PCA modules in the capture mode, either one or both the CCAPM bits CAPN and CAPP for that module must be set ...
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... PCA Timer/Counter FIGURE 8-3: PCA Compare Mode (Software Timer) ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD If necessary, a new 16-bit compare value can be loaded into CCAPnH and CCAPnL during the interrupt routine. The user should be aware that the hardware temporarily disables the comparator function while these registers are being updated so that an invalid match will not occur ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 8.3.3 High Speed Output Mode The high speed output mode is used to toggle a port pin when a match occurs between the PCA timer and the pre- loaded value in the compare registers. In this mode, the CEX output pin (on port 1) associated with the PCA mod- ...
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... Auto-Reload External Input (Max) ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD loaded into the high byte (CCAPnH). Since writes to the CCAPnH register are asynchronous, a new value written to the high byte will not be shifted into CCAPnL for compari- son until the next period of the output (when CL rolls over from 255 to 00) ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 8.3.5 Watchdog Timer The Watchdog Timer mode is used to improve reliability in the system without increasing chip count (See Figure 8-6). Watchdog Timers are useful for systems that are suscepti- ble to noise, power glitches, or electrostatic discharge. It can also be used to prevent a software deadlock. If during the execution of the user’ ...
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... Note Programmed (Bit logic state = 0 Unprogrammed (Bit logic state = 1 Not Locked Hard locked Soft locked ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD issued through the command mailbox register, SFCM, exe- cuted from a Locked (hard locked or soft locked) block, can be operated on a soft locked block: Block-Erase, Sector- Erase, Byte-Program and Byte-Verify ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD TABLE 9-1: Security Lock Options Security Lock Bits Level SFST[7:5] SB1 1 000 U 2 100 P 3 011 U 101 P 010 U 110 P 001 U 4 111 Programmed (Bit logic state = 0 Unprogrammed (Bit logic state = 1). 2. SFST[7:5] = Security Lock Status Bits (SB1_i, SB2_i, SB3_i) 9 ...
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... Location of MOVC or IAP instruction 2. Target address is the location of the byte being read 3. External host Byte-Verify access does not depend on a source address. ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD Byte-Verify Allowed Source Target 1 2 Address Address ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 10.0 RESET A system reset initializes the MCU and begins program execution at program memory location 0000H. The reset input for the device is the RST pin. In order to reset the device, a logic level high must be applied to the RST pin for at least two machine cycles (24 clocks), after the oscillator becomes stable ...
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... TF0 T0 IE1 Ext. Int1 TF1 T1 CF/CCFn PCA IE2 Ext. Int. 2 IE3 Ext. Int. 3 TI/RI/SPIF UART/SPI TF2, EXF2 T2 ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD Vector Interrupt Interrupt Address Enable Priority 0003H EX0 PX0/H 004BH EBO PBO/H 000BH ET0 PT0/H 0013H EX1 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 0 INT0# IT0 1 BOF TF0 0 INT1# IT1 1 TF1 ECF CF CCFn ECCFn 0 INT2# IT2 1 0 INT3# IT3 SPIF SPIE TF2 EXF2 INDIVIDUAL ENABLES FIGURE 11-1: Interrupt Structure ©2007 Silicon Storage Technology, Inc. IP/IPH/IPA/IPAH IE & IEA REGISTERS REGISTERS IE0 IE1 ...
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... Mode (Set PD bit in PCON) MOV PCON, #02H; ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD 12.2 Power-down Mode The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode, the clock is stopped and external interrupts are active for level sensitive interrupts only ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 13.0 SYSTEM CLOCK AND CLOCK OPTIONS 13.1 Clock Input Options and Recom- mended Capacitor Values for Oscillator Shown in Figure 13-1 are the input and output of an inter- nal inverting amplifier (XTAL1, XTAL2), which can be con- figured for use as an on-chip oscillator. ...
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... Supply Voltage DD SST89V5xRD2/RD f Oscillator Frequency OSC SST89V5xRD2/RD Oscillator Frequency for IAP SST89V5xRD2/RD ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ -1. 25° 1. 260°C for 10 seconds ° C capable in both non-Pb and with-Pb solder versions. ° C for 10 seconds; please consult the factory for the latest information. ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD TABLE 14-2: Reliability Characteristics Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 14-3: AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns Output Load ...
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... RST Pull-down Resistor RST 6 C Pin Capacitance IO I Power Supply Current DD IAP Mode @ 33 MHz Active Mode @ 33 MHz Idle Mode @ 33 MHz Power-down Mode ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD = 2.7-3.6V Test Conditions 2.7 < V < 3.6 DD 2.7 < V < 3.6 DD 2.7 < V < 3 2.7V ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 1. Under steady state (non-transient) conditions, I Maximum I per port pin: 15mA OL Maximum I per 8-bit port: 26mA OL Maximum I total for all outputs: 71mA exceeds the test condition listed test conditions. 2. Capacitive loading on Ports 0 and 2 may cause spurious noise to be superimposed on the V due to external bus capacitance discharging into the Port 0 and 2 pins when the pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > ...
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... Data Sheet FIGURE 14-1: I vs. Frequency for 3V SST89V5xRD2/RD DD ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD Maximum Active I DD Maximum Idle I Typical Active I DD Typical Idle Internal Clock Frequency (MHz) 66 FlashFlex MCU S71255-10-000 12/07 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 14.2 AC Electrical Characteristics AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE#, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 14-7: AC Electrical Characteristics ( -40°C to +85° Symbol Parameter 1/T x1 Mode Oscillator Frequency CLCL 1/2T ...
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... L: Logic level LOW or ALE P: PSEN# For example Time from Address Valid to ALE Low AVLL T = Time from ALE Low to PSEN# Low LLPL ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD = 2.7-3.6V@33MHz, 4.5-5.5V@40MHz Oscillator 33 MHz (x1 Mode) 40 MHz (x1 Mode MHz (x2 Mode) 20 MHz (x2 Mode) Min Max ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD T LHLL ALE PSEN# PORT 0 PORT 2 FIGURE 14-2: External Program Memory Read Cycle T LHLL ALE PSEN# RD# T AVLL A0-A7 FROM RI or DPL PORT 0 PORT 2 FIGURE 14-3: External Data Memory Read Cycle ©2007 Silicon Storage Technology, Inc. T PLPH T LLIV ...
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... High Time CHCX T Low Time CLCX T Rise Time CLCH T Fall Time CHCL V - 0.5 DD 0.45 V FIGURE 14-5: External Clock Drive Waveform ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ WLWH LLWL T QVWX LLAX QVWH DATA OUT T AVWL P2[7:0] or A8-A15 FROM DPH 40MHz Min ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD TABLE 14-9: Serial Port Timing Symbol Parameter T Serial Port Clock Cycle Time XLXL T Output Data Setup to Clock Rising Edge QVXH T Output Data Hold After Clock Rising Edge XHQX T Input Data Hold After Clock Rising Edge XHDX T Clock Rising Edge to Input Data Valid ...
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... XTAL2 CLOCK XTAL1 SIGNAL V SS All other pins disconnected FIGURE 14-11: I Test Condition, DD Idle Mode ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/RD TO TESTER 1255 F42 1255 F43.1 All other pins disconnected FIGURE 14-12: I TABLE 14-10: Flash Memory Programming Parameter I DD ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 15.0 PRODUCT ORDERING INFORMATION Device Speed Suffix1 SST89x5xRDx - XX - ©2007 Silicon Storage Technology, Inc. Suffix2 Package Attribute non-Pb Package Modifier pins pins Package Type P = PDIP N = PLCC TQ = TQFP Operation Temperature C = Commercial = 0°C to +70° Industrial = -40°C to +85°C Operating Frequency ...
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... Data Sheet 15.1 Valid Combinations Valid combinations for SST89V54RD2 SST89V54RD2-33-C-NJE SST89V54RD2-33-C-TQJE SST89V54RD2-33-I-NJE SST89V54RD2-33-I-TQJE Valid combinations for SST89V58RD2 SST89V58RD2-33-C-NJE SST89V58RD2-33-C-TQJE SST89V58RD2-33-I-NJE SST89V58RD2-33-I-TQJE Valid combinations for SST89V54RD SST89V54RD-33-C-PIE Valid combinations for SST89V58RD SST89V58RD-33-C-PIE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD 16.0 PACKAGING DIAGRAMS 40 1 Pin #1 Identifier .065 .075 Base Plane Seating Plane .015 Min. .063 .045 .090 .055 Note: 1. Complies with JEDEC publication 95 MS-011 AC dimensions (except as noted), although some dimensions may be more stringent. † = JEDEC min is .115; SST min is less stringent 2 ...
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... Coplanarity: 0.1 (±0.05) mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm. FIGURE 16-3: 44-lead Thin Quad Flat Pack (TQFP) SST Package Code: TQJ ©2007 Silicon Storage Technology, Inc. SST89V54RD2/RD / SST89V58RD2/ 10.00 ± 0.10 12.00 ± 0.25 23 ...
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... FlashFlex MCU SST89V54RD2/RD / SST89V58RD2/RD TABLE 16-1: Revision History Number 00 • Initial Release 01 • Changed MPNs of SST89E/V5xRD2 PDIP devices to SST89E/V5xRD • Removed SST89E/V516RD2 devices and associated MPNs • Removed all industrial temperature PDIP devices and associated MPNs • Clarified Surface Mount Temperatures in “Absolute Maximum Stress Ratings” on page 62 • ...