AT32UC3C164C-AUR Atmel, AT32UC3C164C-AUR Datasheet

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AT32UC3C164C-AUR

Manufacturer Part Number
AT32UC3C164C-AUR
Description
IC MCU AVR32 64K FLASH 100TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3C164C-AUR

Core Processor
AVR
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
81
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x12b, D/A 4x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

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Part Number:
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Manufacturer:
ATMEL
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Part Number:
AT32UC3C164C-AUR
Manufacturer:
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Quantity:
10 000
Features
High Performance, Low Power 32-bit AVR
Multi-hierarchy Bus System
Internal High-Speed Flash
Internal High-Speed SRAM, Single-Cycle Access at Full Speed
External Memory Interface on AT32UC3C0 Derivatives
Interrupt Controller
System Functions
Windowed Watchdog Timer (WDT)
Asynchronous Timer (AST) with Real-Time Clock Capability
Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
Ethernet MAC 10/100 Mbps interface
Universal Serial Bus (USB)
One 2-channel Controller Area Network (CAN)
– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
– Built-in Floating-Point Processing Unit (FPU)
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing 1.49 DMIPS / MHz
– Memory Protection Unit
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 16 Peripheral DMA Channels Improves Speed for Peripheral Communication
– 512 Kbytes, 256 Kbytes, 128 Kbytes, 64 Kbytes Versions
– Single Cycle Access up to 33 MHz
– FlashVault
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
– 64 Kbytes (512 KB and 256 KB Flash), 32 Kbytes (128 KB Flash), 16 Kbytes (64 KB
– 4 Kbytes on the Multi-Layer Bus System (HSB RAM)
– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)
– Autovectored Low Latency Interrupt Service with Programmable Priority
– Power and Clock Manager
– Internal 115KHz (RCSYS) and 8MHz/1MHz (RC8M) RC Oscillators
– One 32 KHz and Two Multipurpose Oscillators
– Clock Failure detection
– Two Phase-Lock-Loop (PLL) allowing Independent CPU Frequency from USB or
– Counter or Calendar Mode Supported
– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)
– Device 2.0 and Embedded Host Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
– CAN2A and CAN2B protocol compliant, with high-level mailbox system
– Two independent channels, 16 Message Objects per Channel
User Applications
Flash)
CAN Frequency
• Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State)
• Up to 49 DMIPS Running at 33 MHz from Flash (0 Wait-State)
Technology Allows Pre-programmed Secure Library Support for End
®
Microcontroller
32-bit AVR
Microcontroller
AT32UC3C0512C
AT32UC3C0256C
AT32UC3C0128C
AT32UC3C064C
AT32UC3C1512C
AT32UC3C1256C
AT32UC3C1128C
AT32UC3C164C
AT32UC3C2512C
AT32UC3C2256C
AT32UC3C2128C
AT32UC3C264C
Preliminary
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
32117BS–AVR–03/11
®

Related parts for AT32UC3C164C-AUR

AT32UC3C164C-AUR Summary of contents

Page 1

... Two independent channels, 16 Message Objects per Channel ® Microcontroller ® 32-bit AVR Microcontroller AT32UC3C0512C AT32UC3C0256C AT32UC3C0128C AT32UC3C064C AT32UC3C1512C AT32UC3C1256C AT32UC3C1128C AT32UC3C164C AT32UC3C2512C AT32UC3C2256C AT32UC3C2128C AT32UC3C264C Preliminary Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 32117BS–AVR–03/11 ...

Page 2

One 4-Channel 20-bit Pulse Width Modulation Controller (PWM) – Complementary outputs, with Dead Time Insertion – Output Override and Fault Protection • Two Quadrature Decoders • One 16-channel 12-bit Pipelined Analog-To-Digital Converter (ADC) – Dual Sample and Hold Capability ...

Page 3

Description The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on ...

Page 4

... The analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers ...

Page 5

Overview 2.1 Block diagram Figure 2- 32117BS–AVR-03/11 Block diagram aWire RESET_N TDO JTAG TCK NEXUS TDI INTERFACE TMS CLASS 2+ MEMORY PROTECTION UNIT MCKO OCD MDO[5..0] INSTR MSEO[1..0] INTERFACE EVTI_N EVTO_N VBUS D+ USB D- ...

Page 6

... RMII/MII Crystal Oscillator 0.4-20 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) 0.4-20 MHz (OSC1 AT32UC3C AT32UC3C1512C/ AT32UC3C2512C/ AT32UC3C1256C/ AT32UC3C2256C/ AT32UC3C1128C/ AT32UC3C2128C/ AT32UC3C164C AT32UC3C264C 512/256/128/64 KB 512/256/128/64 KB 64/64/32/16KB 64/64/32/16KB RMII/MII MII only 4x2 PLL 80-240 MHz (PLL0/PLL1) RC Oscillator 115 kHz (RCSYS) RC Oscillator 8 MHz (RC8M) ...

Page 7

... Table 2-1. Feature Analog Comparators JTAG aWire Max Frequency Package 32117BS–AVR-03/11 Configuration Summary AT32UC3C0512C/ AT32UC3C0256C/ AT32UC3C0128C/ AT32UC3C064C 4 LQFP144 AT32UC3C AT32UC3C1512C/ AT32UC3C2512C/ AT32UC3C1256C/ AT32UC3C2256C/ AT32UC3C1128C/ AT32UC3C2128C/ AT32UC3C164C AT32UC3C264C MHz TQFP100 TQFP64/QFN64 7 ...

Page 8

Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Figure 3-1. QFN64/TQFP64 Pinout Note: 32117BS–AVR-03/11 on QFN packages, the exposed pad is unconnected. AT32UC3C Table 3-1 on page 11. 8 ...

Page 9

Figure 3-2. TQFP100 Pinout 32117BS–AVR-03/11 AT32UC3C 9 ...

Page 10

Figure 3-3. LQFP144 Pinout 32117BS–AVR-03/11 AT32UC3C 10 ...

Page 11

Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing TQFP ...

Page 12

Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN PA19 PA20 PA21 PA22 22 22 ...

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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN O 14 PB11 43 15 PB12 44 16 PB13 45 17 PB14 46 18 PB15 47 19 PB16 48 20 PB17 49 ...

Page 14

Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN PC02 PC03 PC04 PC05 69 57 ...

Page 15

Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN PC24 88 98 PC25 89 99 PC26 90 100 PC27 91 101 PC28 92 102 PC29 93 105 PC30 ...

Page 16

Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN O 124 PD15 111 125 PD16 112 126 PD17 113 127 PD18 114 128 PD19 115 129 PD20 116 57 88 130 ...

Page 17

Table 3-2. Function aWire DATAOUT JTAG port connections Oscillators 3.2.3 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF ...

Page 18

OCD AXS register. For details, see the AVR32UC Techni- cal Reference Manual. Table 3-5. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] 3.2.6 Other Functions The functions listed in pin ...

Page 19

Table 3-7. Signal Description List Signal Name Function VDDIN_5 1.8V Voltage Regulator Input VDDIN_33 USB I/O power supply VDDCORE 1.8V Voltage Regulator Output GNDIO1 GNDIO2 I/O Ground GNDIO3 GNDANA Analog Ground GNDCORE Ground of the core GNDPLL Ground of the ...

Page 20

Table 3-7. Signal Description List Signal Name Function Analog negative reference connected to ADCVREFN external capacitor MCKO Trace Data Output Clock MDO[5:0] Trace Data Output MSEO[1:0] Trace Frame Control EVTI_N Event In EVTO_N Event Out DATA aWire data DATAOUT aWire ...

Page 21

Table 3-7. Signal Description List Signal Name Function SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDWE SDRAM Write Enable EXTINT[8:1] External Interrupt Pins NMI_N = EXTINT[0] Non-Maskable Interrupt Pin General Purpose Input/Output - GPIOA, GPIOB, GPIOC, GPIOD PA[29:19] - PA[16:0] ...

Page 22

Table 3-7. Signal Description List Signal Name Function RX_CLK Receive Clock RX_DV Receive Data Valid RX_ER Receive Coding Error SPEED Speed TXD[3:0] Transmit Data TX_CLK Transmit Clock or Reference Clock TX_EN Transmit Enable TX_ER Transmit Coding Error WOL Wake-On-LAN PAD_EVT[15:0] ...

Page 23

Table 3-7. Signal Description List Signal Name Function NPCS[3:0] SPI Peripheral Chip Select SCK Clock A0 Channel 0 Line A A1 Channel 1 Line A A2 Channel 2 Line A B0 Channel 0 Line B B1 Channel 1 Line B ...

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Table 3-7. Signal Description List Signal Name Function DP USB Device Port Data + VBUS USB VBUS Monitor and OTG Negociation ID ID Pin of the USB Bus VBOF USB VBUS On/off: bus power control port 3.4 I/O Line Considerations ...

Page 25

Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...

Page 26

Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack ...

Page 27

Figure 4-1. Instruction memory controller 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) ...

Page 28

Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...

Page 29

Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically ...

Page 30

Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...

Page 31

Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Priority N/A N/A Mode changes can ...

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Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code ...

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Table 4-3. Reg # 33- ...

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Table 4-3. Reg # 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as ...

Page 35

EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments ...

Page 36

Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism ...

Page 37

An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since ...

Page 38

Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x80000000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...

Page 39

Memories 5.1 Embedded Memories • Internal High-Speed Flash (See – 512 Kbytes – 256 Kbytes – 128 Kbytes – 64 Kbytes • Internal High-Speed SRAM, Single-cycle access at full speed (See – 64 Kbytes – 32 Kbytes – 16 ...

Page 40

Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented translation, as described ...

Page 41

... Table 5-2. Part Number AT32UC3C0512C AT32UC3C1512C AT32UC3C2512C AT32UC3C0256C AT32UC3C1256C AT32UC3C2256C AT32UC3C0128C AT32UC3C1128C AT32UC3C2128C AT32UC3C064C AT32UC3C164C AT32UC3C264C 5.3 Peripheral Address Map Table 5-3. Peripheral Address Mapping Address 0xFFFD0000 0xFFFD1000 0xFFFD1400 0xFFFD1800 0xFFFD1C00 0xFFFD2000 0xFFFD2400 0xFFFD2800 0xFFFD2C00 0xFFFD3000 32117BS–AVR-03/11 Flash Memory Parameters ...

Page 42

Table 5-3. Peripheral Address Mapping 0xFFFE0000 0xFFFE1000 0xFFFE2000 0xFFFE2400 0xFFFE2800 0xFFFE2C00 0xFFFE3000 0xFFFF0000 0xFFFF0400 0xFFFF0800 0xFFFF0C00 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF2000 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 32117BS–AVR-03/11 HFLASHC Flash Controller - HFLASHC USBC USB 2.0 OTG Interface - USBC HMATRIX HSB Matrix ...

Page 43

Table 5-3. Peripheral Address Mapping 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 0xFFFF4800 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 0xFFFF5C00 0xFFFF6000 0xFFFF6400 0xFFFF6800 0xFFFF6C00 0xFFFF7000 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, ...

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The following GPIO registers are mapped on the local bus: Table 5-4. Port 32117BS–AVR-03/11 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register ...

Page 45

Table 5-4. Port D 32117BS–AVR-03/11 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) AT32UC3C Local Bus Mode Address Access WRITE 0x40000340 Write-only SET 0x40000344 Write-only CLEAR 0x40000348 Write-only TOGGLE ...

Page 46

Supply and Startup Considerations 6.1 Supply Considerations 6.1.1 Power Supplies The AT32UC3C has several types of power supply pins: • VDDIO pins (VDDIO1, VDDIO2, VDDIO3): Power I/O lines. Two voltage ranges are available 3.3V nominal. The VDDIO ...

Page 47

Figure 6-1 on page 47 I/O lines and analog blocks will be powered by the same power (VDDIN_5 = VDDIO1 = VDDIO2 = VDDIO3 = VDDANA). Figure 6-1. C IN2 6.1.3.2 3.3V Single Supply Mode In 3.3V single supply mode, ...

Page 48

Figure 6-2. C IN2 6.1.4 Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Recommended order for power supplies is also described in this ...

Page 49

Startup Considerations This chapter summarizes the boot sequence of the AT32UC3C. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.2.1 Starting of clocks At power-up, the BOD33 and ...

Page 50

Electrical Characteristics 7.1 Absolute Maximum Ratings* Operating temperature..................................... -40°C to +85°C Storage temperature...................................... -60°C to +150°C Voltage on any pin except DM/DP/VBUS with respect to ground ............................ -0. Voltage on DM/DP with respect to ground.........-0.3V to +3.6V ...

Page 51

Table 7-2. Supply Rise Rates and Order Symbol Parameter V DC supply internal 3.3V regulator VDDIN_5 V DC supply internal 1.8V regulator VDDIN_33 V VDDIO1 V DC supply peripheral I/O VDDIO2 V VDDIO3 DC supply peripheral I/O and V VDDANA ...

Page 52

Internal 3.3V regulator is off • 25°C A • I/Os are configured as inputs, with internal pull-up enabled. • Oscillators – OSC0/1 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) stopped – PLL0 running – PLL1 stopped ...

Page 53

Figure 7-1. 7.4.1 Peripheral Power Consumption The values in conditions. • Operating conditions core supply – V – V – V – V – Internal 3.3V regulator is off. • 25°C A • I/Os are configured as inputs, ...

Page 54

PLL1 stopped • Clocks – External clock on XIN0 as main clock source. – CPU, HSB, and PB clocks undivided Consumption active is the added current consumption when the module clock is turned on and when the module is ...

Page 55

I/O Pin Characteristics Table 7-6. Normal I/O Pin Characteristics Symbol Parameter R Pull-up resistance PULLUP R Pull-down resistance PULLDOWN Input low-level V IL voltage Input high-level V IH voltage Output low-level V OL voltage Output high-level V OH voltage ...

Page 56

Table 7-6. Normal I/O Pin Characteristics Symbol Parameter (3) t Rise time RISE (3) t Fall time FALL I Input leakage current LEAK C Input capacitance IN Note corresponds to either V VDD on page 11 for details. ...

Page 57

Oscillator Characteristics 7.6.1 Oscillator (OSC0 and OSC1) Characteristics 7.6.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN0 or XIN1. Table 7-7. Digital Clock Characteristics Symbol Parameter f ...

Page 58

Table 7-8. Crystal Oscillator Characteristics Symbol Parameter f Crystal oscillator frequency OUT C Internal equivalent load capacitance i t Startup time STARTUP Notes: 1. Please refer to the SCIF chapter for details. 7.6.2 32KHz Crystal Oscillator (OSC32K) Characteristics 7.6.2.1 Digital ...

Page 59

Phase Lock Loop (PLL0 and PLL1) Characteristics Table 7-11. PLL Characteristics Symbol Parameter f Output frequency VCO f Input frequency IN I Current consumption PLL Startup time, from enabling t the PLL until the PLL is STARTUP locked 7.6.4 ...

Page 60

Flash Characteristics Table 7-15 wait states. The FSW bit in the FLASHC FSR register controls the number of wait states used when accessing the flash memory. Table 7-15. Maximum Operating Frequency Flash Wait States 0 1 Table 7-16. Flash ...

Page 61

Analog Characteristics 7.8.1 1.8V Voltage Regulator Characteristics Table 7-18. 1.8V Voltage Regulator Electrical Characteristics Symbol Parameter V Input voltage range VDDIN_5 V Output voltage, calibrated value VDDCORE V Output voltage accuracy ACCURACY I DC output current OUT I Static ...

Page 62

Brown Out Detector (BOD18) Characteristics The values in Table 7-21. BODLEVEL Value 7.8.4 3.3V Brown Out Detector (BOD33) Characteristics The values in Table 7-23. BOD33.LEVEL Value ...

Page 63

Brown Out Detector (BOD50) Characteristics The values in Table 7-25. BOD50.LEVEL Value 32117BS–AVR-03/11 Table 7-25 describe the values of the BOD50.LEVEL field in the SCIF module. BOD50.LEVEL Values Parameter AT32UC3C Min Max ...

Page 64

Analog to Digital Converter (ADC) and sample and hold (S/H) Characteristics Table 7-27. ADC and S/H characteristics Symbol Parameter Conditions 12-bit resolution mode, V 10-bit resolution mode, V 8-bit resolution mode, V ADC clock f ADC frequency 12-bit resolution ...

Page 65

Table 7-30. ADC Inputs Symbol Parameter V ADC input voltage range ADCINn C Internal Capacitance ONCHIP R Switch resistance ONCHIP Figure 7-3. Table 7-31. ADC Transfer Characteristics 12-bit Resolution Mode Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity ...

Page 66

Table 7-32. ADC Transfer Characteristics 10-bit Resolution Mode Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: 1. The measures are done ...

Page 67

Table 7-34. ADC and S/H Transfer Characteristics (Continued)12-bit Resolution Mode and S/H gain = 1 Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-Linearity Offset error Gain error Note: 1. The measures are done without any I/O activity on ...

Page 68

Figure 7-4. Table 7-38. Transfer Characteristics Symbol Parameter RES Resolution INL Integral Non-Linearity DNL Differential Non-linearity Offset error Gain error RES Resolution INL Integral Non-Linearity DNL Differential Non-linearity Offset error Gain error Note: 1. The measures are done without any ...

Page 69

Analog Comparator Characteristics Table 7-39. Analog Comparator Characteristics Symbol Parameter Positive input voltage range Negative input voltage range V Offset OFFSET V Hysteresis HYST t Propagation delay DELAY t Start-up time STARTUP Note: 1. The measures are done without ...

Page 70

Timing Characteristics 7.9.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula CONST Where t CPU clock the startup time of the oscillator, stop, deepstop, and static sleep ...

Page 71

Figure 7-5. Voltage BOD33 threshold at power-up BOD18 threshold at power-up Internal Reset Time Reset 7.9.2 RESET_N characteristics Table 7-43. RESET_N Clock Waveform Parameters Symbol Parameter t RESET_N minimum pulse length RESET 32117BS–AVR-03/11 Startup and Reset Time Startup Time from ...

Page 72

USART in SPI Mode Timing 7.9.3.1 Master mode Figure 7-6. Figure 7-7. Table 7-44. USART in SPI Mode Timing, Master Mode Symbol Parameter USPI0 MISO setup time before SPCK rises USPI1 MISO hold time after SPCK rises USPI2 SPCK ...

Page 73

Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: Where the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. ...

Page 74

Figure 7-9. Figure 7-10. USART in SPI Slave Mode NPCS Timing USPI12 SPCK, CPOL=0 SPCK, CPOL=1 USPI14 NSS Table 7-45. USART in SPI mode Timing, Slave Mode Symbol Parameter USPI6 SPCK falling to MISO delay USPI7 MOSI setup time before ...

Page 75

Maximum SPI Frequency, Slave Input Mode The maximum SPI slave input frequency is given by the following formula: Where on CPOL and NCPHA. chapter for a description of this clock. Maximum SPI Frequency, Slave Output Mode The maximum SPI slave ...

Page 76

Figure 7-12. SPI Master Mode With (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) Table 7-46. SPI Timing, Master Mode Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after SPCK rises SPI2 ...

Page 77

Slave mode Figure 7-13. SPI Slave Mode With (CPOL= 0 and NCPHA (CPOL= 1 and NCPHA= 0) Figure 7-14. SPI Slave Mode With (CPOL= NCPHA (CPOL= NCPHA= 1) Figure 7-15. SPCK, CPOL=0 SPCK, CPOL=1 NPCS ...

Page 78

Table 7-47. SPI Timing, Slave Mode Symbol Parameter SPI6 SPCK falling to MISO delay SPI7 MOSI setup time before SPCK rises SPI8 MOSI hold time after SPCK rises SPI9 SPCK rising to MISO delay SPI10 MOSI setup time before SPCK ...

Page 79

TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more information . Table 7-48. TWI-Bus Timing Requirements Symbol Parameter t TWCK and TWD rise time r t TWCK and TWD fall time f t ...

Page 80

JTAG Timing Figure 7-16. JTAG Interface Signals Scan Inputs Scan Outputs (1) Table 7-49. JTAG Timings Symbol Parameter JTAG0 TCK Low Half-period JTAG1 TCK High Half-period JTAG2 TCK Period JTAG3 TDI, TMS Setup before TCK High JTAG4 TDI, TMS ...

Page 81

EBI Timings See EBI I/O lines description for more details. Table 7-50. SMC Clock Signal. Symbol Parameter 1/(t ) SMC Controller clock frequency CPSMC Note: 1. The maximum frequency of the SMC interface is the same as the max ...

Page 82

Table 7-52. SMC Read Signals with no Hold Settings Symbol Parameter SMC Data setup before NRD high 19 SMC Data hold after NRD high 20 SMC Data setup before NCS high 21 SMC Data hold after NCS high 22 Note: ...

Page 83

Table 7-54. SMC Write Signals with No Hold Settings (NWE Controlled only) Symbol Parameter SMC NWE rising to A2-A25 valid 37 SMC NWE rising to NBS0/A0 valid 38 SMC NWE rising to A1/NBS2 change 40 SMC NWE rising to NCS ...

Page 84

Figure 7-18. SMC Signals for NRD and NRW Controlled Accesses A2-A25 A0/A1/NBS[3:0] NCS SMC9 NRD SMC19 D0 - D15 NWE Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same pro- cess ...

Page 85

Table 7-56. SDRAM Signal Symbol Parameter SDRAMC SDCKE high before SDCK rising edge 1 SDRAMC SDCKE low after SDCK rising edge 2 SDRAMC SDCKE low before SDCK rising edge 3 SDRAMC SDCKE high after SDCK rising edge 4 SDRAMC ...

Page 86

Figure 7-19. SDRAMC Signals relative to SDCK. SDCK SDRAMC SDRAMC SDRAMC 1 2 SDCKE SDCS RAS CAS SDWE SDA10 A0 - A9, A11 - A13 BA0/BA1 DQM0 - DQM3 D0 - D15 Read D0 - D15 to Write 32117BS–AVR-03/11 SDRAMC ...

Page 87

MACB Characteristics Table 7-57. Ethernet MAC Signals Symbol Parameter MAC Setup for MDIO from MDC rising 1 MAC Hold for MDIO from MDC rising 2 MAC MDIO toggling from MDC falling 3 Note: 1. These values are based on ...

Page 88

Figure 7-20. Ethernet MAC MII Mode MDC MDIO COL CRS TX_CLK TX_ER TX_EN TXD[3:0] RX_CLK RXD[3:0] RX_ER RX_DV 32117BS–AVR-03/11 MAC MAC 1 2 MAC MAC 4 5 MAC MAC 6 7 MAC MAC 11 12 MAC MAC 13 14 MAC ...

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Table 7-59. Ethernet MAC RMII Specific Signals Symbol Parameter MAC TX_EN toggling from TX_CLK rising 21 MAC TXD toggling from TX_CLK rising 22 MAC Setup for RXD from TX_CLK 23 MAC Hold for RXD from TX_CLK 24 MAC Setup for ...

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Mechanical Characteristics 8.1 Thermal Considerations 8.1.1 Thermal Data Table 8-1 Table 8-1. Symbol θ JA θ JC θ JA θ JC θ JA θ JC θ JA θ JC 8.1.2 Junction Temperature The average chip-junction temperature ...

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Package Drawings Figure 8-1. QFN-64 package drawing Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 8-2. Device and Package Maximum Weight 200 Table 8-3. Package ...

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Figure 8-2. TQFP-64 package drawing Table 8-5. Device and Package Maximum Weight 300 Table 8-6. Package Characteristics Moisture Sensitivity Level Table 8-7. Package Reference JEDEC Drawing Reference JESD97 Classification 32117BS–AVR-03/11 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3C 92 ...

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Figure 8-3. TQFP-100 package drawing Table 8-8. Device and Package Maximum Weight 500 Table 8-9. Package Characteristics Moisture Sensitivity Level Table 8-10. Package Reference JEDEC Drawing Reference JESD97 Classification 32117BS–AVR-03/11 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3C 93 ...

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Figure 8-4. LQFP-144 package drawing Table 8-11. Device and Package Maximum Weight 1300 Table 8-12. Package Characteristics Moisture Sensitivity Level Table 8-13. Package Reference JEDEC Drawing Reference JESD97 Classification 32117BS–AVR-03/11 mg Jdec J-STD0-20D - MSL 3 MS-026 E3 AT32UC3C 94 ...

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Soldering Profile Table 8-14 Table 8-14. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within 5⋅C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25⋅C to Peak Temperature ...

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... AT32UC3C0256C-ALUT AT32UC3C0256C AT32UC3C0256C-ALUR AT32UC3C0128C-ALUT AT32UC3C0128C AT32UC3C0128C-ALUR AT32UC3C064C-ALUT AT32UC3C064C AT32UC3C064C-ALUR AT32UC3C1512C-AUT AT32UC3C1512C AT32UC3C1512C-AUR AT32UC3C1256C-AUT AT32UC3C1256C AT32UC3C1256C-AUR AT32UC3C1128C-AUT AT32UC3C1128C AT32UC3C1128C-AUR AT32UC3C164C-AUT AT32UC3C164C AT32UC3C164C-AUR AT32UC3C2512C-A2UT AT32UC3C2512C-A2UR AT32UC3C2512C AT32UC3C2512C-Z2UT AT32UC3C2512C-Z2UR AT32UC3C2256C-A2UT AT32UC3C2256C-A2UR AT32UC3C2256C AT32UC3C2256C-Z2UT AT32UC3C2256C-Z2UR AT32UC3C2128C-A2UT AT32UC3C2128C-A2UR AT32UC3C2128C AT32UC3C2128C-Z2UT AT32UC3C2128C-Z2UR AT32UC3C264C-A2UT AT32UC3C264C-A2UR AT32UC3C264C AT32UC3C264C-Z2UT AT32UC3C264C-Z2UR 32117BS– ...

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Errata 10.1 rev E 10.1.1 AST 1 AST wake signal is released one ast clock cycle after the busy register is cleared After writing to the Status Clear Register (SCR) the wake signal is released one AST clock cycle ...

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SCIF.PLL0LOCK bit can be used as a valid indication that the PLL is locked. 10.1.5 SPI 1 SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module ...

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TWIS 1 Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg- ister (SR) before the end ...

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D 10.2.1 AST 1 AST wake signal is released one ast clock cycle after the busy register is cleared After writing to the Status Clear Register (SCR) the wake signal is released one AST clock cycle after the ...

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PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig- nal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not ...

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Fix/Workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 10.2 Channel chaining skips first pulse for upper channel When chaining two channels using ...

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USBC 1 UPINRQx.INRQ field is limited to 8-bits In Host mode, when using the UPINRQx.INRQ feature together with the multi-packet mode to launch a finite number of packet among multi-packet, the multi-packet size (located in the descriptor table) is ...

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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. B – 03/ ...

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Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 Package and Pinout ................................................................................. 8 4 Processor and Architecture .................................................................. 25 5 Memories ................................................................................................ 41 6 Supply and Startup Considerations ..................................................... 48 7 Electrical Characteristics ...................................................................... 52 8 Mechanical Characteristics ................................................................... ...

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Ordering Information ............................................................................. 76 10 Errata ....................................................................................................... 77 11 Datasheet Revision History .................................................................. 80 32117BS–AVR-03/11 8.1 Thermal Considerations ..................................................................................70 8.2 Package Drawings ...........................................................................................71 8.3 Soldering Profile ..............................................................................................75 10.1 rev D ................................................................................................................77 11.1 Rev. A – 10/10 .................................................................................................80 AT32UC3C 106 ...

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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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