MC9S08JE64CLH Freescale Semiconductor, MC9S08JE64CLH Datasheet
MC9S08JE64CLH
Specifications of MC9S08JE64CLH
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MC9S08JE64CLH Summary of contents
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... IIC— 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. Document Number: MC9S08JE128 64-LQFP 10mm x 10mm byte-by-byte data transfer ...
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... CPU, and all module information. – This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2009-2010. All rights reserved. 2.15 VREF Specifications............................................................. 35 3 Ordering Information......................................... 41 3 ...
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... Programmable Delay Block (PDB) SAR ADC differential channels SAR ADC single-ended channels Voltage reference output pin (VREFO) 1 Port I/O count does not include two (2) output-only and one (1) input-only pins. 2 Each differential channel is comprised of 2 pin inputs. Freescale Semiconductor Feature MC9S08JE128 81 131072 ...
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... Cyclic Redundancy Check (CRC) Keyboard Interrupt (KBI) Voltage Reference (VREF) Voltage Regulator (VREG) Interrupt Request (IRQ) Flash Wrapper GPIO Port Control The block diagram in Figure 1 shows the structure of the MC9S08JE128 series MCU. 4 Table 2. Versions of On-Chip Modules Preliminary — Subject to Change Version Freescale Semiconductor ...
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... Figure 1. MC9S08JE128 series Block Diagram Freescale Semiconductor Preliminary — Subject to Change Devices in the MC9S08JE128 series 5 ...
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... The following two figures show the 64-pin LQFP pinout configuration. PTA0/SS1 IRO PTA4 PTA5 PTA6 PTA7 PTB0 PTB1/BLMS VSSA VREFL NC NC DADP2 NC DADM2 64-LQFP Figure 2. 64-Pin LQFP Preliminary — Subject to Change 48 PTD7/RX1 47 PTD6/TX1 46 PTD5/SCL/TPM1CH3 45 PTD4/SDA/TPM1CH2 44 PTD3/TPM1CH1 43 PTD2/TPM1CH0 42 PTD1/CMPP2/RESET 41 PTD0/BKGD/MS 40 PTC7/KBI2P2/CLKOUT/ADP11 39 PTC6/KBI2P1/PRACMPO/ADP10 38 PTC5/KBI2P0/CMPP1/ADP9 37 PTC4/KBI1P7/CMPP0/ADP8 36 PTC3/KBI1P6/SS2/ADP7 35 PTC2/KBI1P5/SPSCK2/ADP6 34 PTC1/MISO2 33 PTC0/MOSI2 Freescale Semiconductor ...
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... IRO 2 PTA1/KBI1P0/TX1 3 PTA2/KBI1P1/RX1/ADP4 4 PTA3/KBI1P2/ADP5 5 PTA4 6 PTA5 7 PTA6 8 PTA7 9 PTB0 10 PTB1/BLMS 11 VSSA 12 VREFL DADP2 DADM2 Freescale Semiconductor 80-LQFP Figure 3. 80-Pin LQFP Preliminary — Subject to Change Devices in the MC9S08JE128 series PTE4/CMPP3/TPMCLK/IRQ PTE3/KBI2P6 PTE2/KBI2P5 PTE1/KBI2P4 PTE0/KBI2P3 PTD7/RX1 PTD6/TX1 PTD5/SCL/TPM1CH3 PTD4/SDA/TPM1CH2 PTD3/TPM1CH1 PTD2/TPM1CH0 PTD1/CMPP2/RESET PTD0/BKGD/MS ...
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... PTC4 VREFH VDDA PTB2 PTB3 Figure 4. 81-Pin MAPBGA Preliminary — Subject to Change PTF4 PTF3 PTE4 PTF1 PTF0 PTE3 PTE5 PTE2 PTE1 PTD5 PTD7 PTE0 PTD2 PTD3 PTD6 PTB7 PTC7 PTD4 PTC0 PTC1 PTC2 PTD0 PTC5 PTC6 PTD1 PTB4 PTB5 Freescale Semiconductor ...
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... DADM3 DADP0 DADM0 VREFO H3 28 — DADP1 H2 29 — DADM1 Freescale Semiconductor Table 3. Package Pin Assignments ALT1 ALT2 ALT3 SS1 — — — — — KBI1P0 TX1 — KBI1P1 RX1 ADP4 KBI1P2 ADP5 — — — — — — — — ...
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... IRQ Preliminary — Subject to Change Composite Pin Name VREFH VDDA VSS2 PTB2/EXTAL1 PTB3/XTAL1 VDD2 PTB4/EXTAL2 PTB5/XTAL2 PTB6/KBI1P3 PTB7/KBI1P4 PTC0/MOSI2 PTC1/MISO2 PTC2/KBI1P5/SPSCK2/ADP6 PTC3/KBI1P6/SS2/ADP7 PTC4/KBI1P7/CMPP0/ADP8 PTC5/KBI2P0/CMPP1/ADP9 PTC6/KBI2P1/PRACMPO/ADP10 PTC7/KBI2P2/CLKOUT/ADP11 PTD0/BKGD/MS PTD1/CMPP2/RESET PTD2TPM1CH0 PTD3/TPM1CH1 PTD4/SDA/TPM1CH2 PTD5/SCL/TPM1CH3 PTD6/TX1 PTD7/RX1 PTE0/KBI2P3 PTE1/KBI2P4 PTE2/KBI2P5 PTE3/KBI2P6 PTE4/CMPP3/TPMCLK/IRQ Freescale Semiconductor ...
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... USB_DP VBUS VSS1 VDD1 PTF6 PTF7 PTG0 B3 — — PTG1 Freescale Semiconductor ALT1 ALT2 ALT3 — — — — — — TX2 — — RX2 — — — — — — RX2 TPM2CH1 — TX2 TPM2CH0 — SCL — — SDA — ...
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... All values shown in the typical column are within this category. Those parameters are derived mainly from simulations. D The classification is shown in the column labeled “C” in the parameter tables where appropriate. 12 NOTE Table 4. Parameter Classifications NOTE Preliminary — Subject to Change Freescale Semiconductor ...
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... This device contains circuitry protecting against damage due to high static voltage or electrical fields; however advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either Freescale Semiconductor Table 5. Absolute Maximum Ratings Rating Symbol ...
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... Four-layer board — 2s2p 81-pin MBGA 80-pin LQFP 64-pin LQFP ) in °C can be obtained from: J × θ ÷ 273° Preliminary — Subject to Change Value Unit °C –40 to 105 –40 to 105 °C 135 °C °C Eqn. 1 and T ( neglected I/O Eqn. 2 Freescale Semiconductor ...
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... Table 8. ESD and Latch-Up Protection Characteristics # Rating 1 Human Body Model (HBM) 2 Machine Model (MM) 3 Charge Device Model (CDM) 4 Latch-up Current 125°C A Freescale Semiconductor × 273°C) + θ × and T can be obtained by solving D J Table 7. ESD and Latch-up Test Conditions Description ...
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... V DD > 2 all digital 0.85 x inputs 2.7 V > ≥ 1.8 V Preliminary — Subject to Change 1 Typ Max Unit C — 3.6 V — — — — — — — — 100 mA D — 0 — 0 — 0 — 100 mA D — — — — Freescale Semiconductor ...
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... C Input Capacitance, all pins RAM retention voltage RAM 18 V POR re-arm voltage POR 19 t POR re-arm time POR Freescale Semiconductor Table 9. DC Characteristics (Continued) Condition all digital inputs, > 2 all digital inputs, 2.7 > V ≥ DD 1.8 V all digital inputs — ...
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... DD — V falling DD — V rising DD — — 11 — and V SS Preliminary — Subject to Change 1 Min Typ Max Unit C 2.11 2.16 2. 2.16 2.23 2. 1.80 1.84 1. 1.88 1.93 1. 2.36 2.46 2. 2.36 2.46 2. 2.11 2.16 2. 2.16 2.23 2. — 50 — 1.15 1.17 1. LVDL . DD Freescale Semiconductor . ...
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... Maximum is highest voltage that POR is guaranteed. 9 Run at 1 MHz bus frequency 10 Low voltage detection and warning limits measured at 1 MHz bus frequency. 11 Factory trimmed 3.0 V, Temp = 25°C DD Freescale Semiconductor range during instantaneous and operating DD > greater than Preliminary — Subject to Change Preliminary Electrical Characteristics ...
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... P 25 TBD mA 105 P –40 to — 105 –40 to — 105 –40 to — 105 –40 to TBD mA C 105 –40 to — 105 –40 to — 105 –40 to — 105 –40 to μA — T 105 –40 to μA — T 105 μA — –40 to μA — T 105 Freescale Semiconductor ...
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... Stop2 mode S2I 6 supply cur- DD rent Stop3 mode No clocks active S3I 7 supply cur- DD rent 1 Data in Typical column was characterized at 3.0 V, 25° typical recommended value. Freescale Semiconductor Bus 1 V (V) Typ DD Freq 3 24 MHz TBD 3 20 MHz TBD 3 8 MHz TBD ...
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... Typical Max Unit — 3.6 V μA — 60 μA — 40 — – 0.3 — — 20.0 mV — μs — 1.0 Freescale Semiconductor — ...
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... Programmable reference generator voltage 13 range 2.8 12-bit DAC Electricals Table 13. DAC 12LV Operating Requirements # Characteristic 1 Supply voltage 2 Reference voltage 3 Temperature Output load capacitance 4 5 Output load current Freescale Semiconductor Table 12. PRACMP Electrical Specifications Symbol Min 1.8 In2 DD25 t — PRGST Vstep –0.25 Vprgout V In ...
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... C µA 100 C 500 µA C (TBD) 200 µs C (TBD) 30 µ µs C 1(TBD) µs C 100 mV C (TBD) — ± 8 LSB C ± 1 LSB C ± 0.5 %FSR C ± 0.5 %FSR C (TBD) — See Typical mV C (TBD) Drift figure that follows. TBD µV/yr C Freescale Semiconductor ...
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... Analog Source AS Resistance 9 f ADC Conversion ADCK 10 Clock Freq 3.0 V, Temp = 25 °C, f Typical values assume V DDAD reference only and are not tested in production potential difference. Freescale Semiconductor Table 15. 12-bit ADC Operating Conditions Conditions Min Typ Absolute 1.8 Delta to V -100 DDAD ...
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... Figure 6. ADC Input Impedance Equivalency Diagram 26 SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad Z AS leakage due to input protection + V ADIN – INPUT PIN INPUT PIN INPUT PIN Preliminary — Subject to Change Z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT ADC SAR ENGINE R ADIN R ADIN R ADIN R ADIN C ADIN Freescale Semiconductor ...
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... Non-Linearity 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Integral 12-bit single-ended mode Non-Linearity 11-bit differential mode 10-bit single-ended mode 9-bit differential mode 8-bit single-ended mode Freescale Semiconductor = V , > 1. REFH DDAD REFL SSAD 1 Symb Min Typ — ...
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... Typical values are for ADCK Preliminary — Subject to Change Max Unit C Comment ±2.0 2 LSB T V ADIN V SSAD ±1.0 T ±1.0 ±0.5 T ±0.5 ±3.5 2 LSB T V ADIN V DDAD ±1.5 T ±1.5 ±0.5 T ±0.5 ±0.5 2 LSB leakage AS In current (refer to DC characteristi cs) — mV/× — — Freescale Semiconductor = = ...
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... This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI crystal/resonator is being used as the reference, this specification assumes it is already running. Freescale Semiconductor Symbol Min t — ...
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... BUS Jitter C Ambient) ° 1 Min Typ Max f 32 — 38.4 lo fhi 1 — 5 fhi 1 — 16 fhi 1 — See Note — — — — 1 — R — 0 — S — 100 — R — — — Freescale Semiconductor . Unit kHz MHz MHz MHz MΩ kΩ kΩ ...
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... See crystal or resonator manufacturer’s recommendation. 4 This parameter is characterized and not tested on each device. 5 Proper PC board layout procedures must be followed to achieve specifications. o Freescale Semiconductor Symbol Low range, low gain (RANGE = 0, HGO = 0) Low range, high gain (RANGE = 0, HGO = 1) High range, low gain (RANGE = 1, ...
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... Preliminary — Subject to Change 1 Min Typical Max C dc — — — 800 990 1500 D (TBD) 100 — — — — D cyc 500 — — D 100 — — 100 — — 1 cyc D 100 — — 1 cyc Freescale Semiconductor Unit MHz μ ...
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... This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case. 4 Timing is shown with respect to 20% V RESET PIN IRQ/KBIPx IRQ/KBIPx Freescale Semiconductor Table 19. Control Timing Parameter 4 , Low Drive Slew rate control ...
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... TPMext t TPMext t clkh t clkl t ICPW t TPMext t clkh t clkl Figure 9. Timer External Clock t ICPW t ICPW Figure 10. Timer Input Capture Pulse Preliminary — Subject to Change Min Max Unit MHz Bus 4 — t cyc 1.5 — t cyc 1.5 — t cyc 1.5 — t cyc Freescale Semiconductor ...
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... All timing is shown with respect to 20% V assumes slew rate control disabled and high drive strength enabled for SPI output pins. 3 Time to data active from high-impedance state. 4 Hold time to high-impedance state. Freescale Semiconductor describe the timing requirements for the SPI system. Table 21. SPI Timing 2 Symbol Min ...
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... LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB BIT BIT MSB OUT Figure 11. SPI Master Timing (CPHA = (2) MSB IN BIT (2) MSB OUT BIT Figure 12. SPI Master Timing (CPHA = 1) Preliminary — Subject to Change 3 LSB IN 12 LSB OUT 3 LSB IN LSB OUT Freescale Semiconductor ...
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... Not defined, but normally MSB of character just received SS (INPUT) SCK (CPOL = 0) (INPUT) SCK (CPOL = 1) (INPUT) MISO SEE (OUTPUT) NOTE 8 MOSI (INPUT) NOTE: 1. Not defined, but normally LSB of character just received Freescale Semiconductor BIT MSB OUT 7 BIT Figure 13. SPI Slave Timing (CPHA = ...
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... Mass 10,000 — D_ret Preliminary — Subject to Change supply. For more detailed DD Typical Max Unit — 3.6 V — 3.6 V — 200 kHz μs — 6. Fcyc 4 t Fcyc 4000 t Fcyc 20,000 t Fcyc — — cycles 100,000 — 100 — years Freescale Semiconductor ...
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... Table 23. Internal USB 3.3 V Voltage Regulator Characteristics # Characteristic 1 Regulator operating voltage 2 VREG output input with internal VREG V USB33 3 disabled 4 VREG Quiescent Current Freescale Semiconductor http://www.usb.org. Symbol Min Typ V 3.9 — regin V 3 3.3 regout ...
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... V — (TBD) — TBD ppm/year — 0.10 µA — 75 µA — 125 µA — 1.1 mA — 100 µV/mA — TBD mV TBD — dB Max Unit C 50 °C C Max Unit C TBD µA C Freescale Semiconductor — Notes Notes ...
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... Ordering Information This appendix contains ordering information for the device numbering system. MC9S08JE128 and MC9S08JE64 devices. Freescale Semiconductor Figure 15. Typical Output vs. Temperature TBD Figure 16. Typical Output vs. V Preliminary — Subject to Change Ordering Information DD 41 ...
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... Table 28. Package Descriptions Abbreviation Designator LQFP LQFP Map PBGA or website (http://www.freescale.com), and enter the appropriate document number (from Preliminary — Subject to Change Table Available Packages 64 LQFP 80 LQFP 81 MAPBGA 64 LQFP Case No. Document No. LH 840F-02 98ASS23234W 98ASS23174W LK 917-01 98ASA10670D MB 1662-01 Freescale Semiconductor ...
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... The following revision history table summarizes changes contained in this document. Rev Date 0 6/2009 Initial release of the Data Sheet. 1 7/2009 Updated MCG and XOSC 2 04/2010 Updated electrical characteristic data. Freescale Semiconductor Description of Changes Average internal reference frequency Preliminary — Subject to Change Revision History . 43 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...