PPC8568EPXAUJJ Freescale Semiconductor, PPC8568EPXAUJJ Datasheet

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... Does not have eTSEC1, eTSEC2, or TLU Note that both the MPC8568E and MPC8567E have their own pin assignment tables. © 2010 Freescale Semiconductor, Inc. All rights reserved. Document Number: MPC8568EEC Rev. 1, 10/2010 Contents 1. MPC8568E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 10 3 ...

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... Core 32-Kbyte L1 32-Kbyte Instruction L1 Data Cache Cache 4x/1x RapidIO and/or and/or x4/x2/x1 PCI Express or x8 PCI Express PCI 32-bit 66 MHz QUICC Engine™ Multi-User RAM Serial DMA & 2 Virtual Dual 32-bit RISC CP DMAs Serial Interface 3 GMII/ 2 UL2/POS 2 RGMII/TBI/RTBI Freescale Semiconductor ...

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... SRAM features include the following: — I/O devices access SRAM regions by marking transactions as snoopable (global). — Regions can reside at any aligned location in the memory map. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 2 C controllers, DUART, and local bus controller (LBC) NOTE ...

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... HDLC/Transparent or 128 channels of SS#7 • Includes support for the following serial interfaces: — Two UL2/POS-PHY interfaces with 124 Multi-PHY addresses on UTOPIA interface each or 31 Multi-PHY addresses on the POS interface each. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with minimal change. Some of the key features of these controllers include: • Flexible configuration for multiple PHY interface configurations. configurations. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor MPC8568E Overview Table 1 lists available 5 ...

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... TBI, GMII, or MII RTBI, RGMII, or RMII 8-bit FIFO TBI, GMII, MII, RTBI, RGMII, RMII, or 8-bit FIFO 16-bit FIFO 1 eTSEC2 TBI, GMII, or MII RTBI, RGMII, or RMII TBI, GMII, MII, RTBI, RGMII, RMII, or 8-bit FIFO 8-bit FIFO Not used/not available Freescale Semiconductor ...

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... Supports PCI-to-memory and memory-to-PCI streaming, memory prefetching of PCI read accesses, and posting of processor-to-PCI and PCI-to-memory writes • PCI 3.3-V compatible with selectable hardware-enforced coherency MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor MPC8568E Overview 7 ...

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... Other features of the PCI Express interface include: • x8, x4, x2, and x1 link widths supported • Selectable operation as root complex or endpoint • Both 32- and 64-bit addressing and 256-byte maximum payload size • Full 64-bit decode with 32-bit wide windows MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... In addition to low-voltage operation and dynamic power management, which automatically minimizes power consumption of blocks when they are idle, four power consumption modes are supported: full on, doze, nap, and sleep. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 2 C, DUART, and Local Bus Controller MPC8568E Overview ...

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... –0.3 to 1.21 V PLAT _ CORE CE, _ PCI, _ LBIU, _ SRDS –0.3 to 1.21 –0 –0 –0.3 to 1.98 –0 –0.3 to 2.75 –0 –0.3 to 2.75 –0 –0 –0.3 to 2.75 Freescale Semiconductor — — V — — — — — ...

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... Core power supply for SerDes transceiver Pad power supply for SerDes transceiver DDR and DDR2 DRAM I/O voltage MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 2 C, and JTAG signals Table 3. Absolute maximum ratings are stress ratings only, and by more than 0 ...

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... V ± 165 2.5 V ± 125 3.3 V ± 165 3.3 V ± 165 mV DD 2.5 V ± 125 mV MV GND GND REF DD LV GND GND GND GND to105 1 CLOCK /GV /LV /TV / Freescale Semiconductor Unit Notes V — V — V — V — V — V — V — V — — ...

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... All supplies must be at their stable values within 50 ms. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Table 3. The input voltage threshold scales with respect to the and LV based receivers are simple CMOS I/O circuits and satisfy DD DD signal (nominally set to GV REF Table 4 ...

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... Maximum Unit 12.0 13.0 W 12.3 13.6 W 15.7 16.9 W 17.2 18 Unit Comment DD 3 Data rate 64-bit with W ECC 60% utilization W W — W — W — W — W — 0.49 W — 0.71 W — Freescale Semiconductor ...

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... AC timing specifications for the MPC8568E. At recommended operating conditions (see Parameter/Condition SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 1.8 V 3 ...

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... CCB . Typical Max Unit Notes — +/– 150 and Section 23.3, . Typical Max Unit — 66.7 MHz — — ns 1.0 2.3 ns — — +/– 150 ps . There is CCB Freescale Semiconductor Notes — — 3,4 ...

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... MHz 4.6 Other Input Clocks For information on the input clocks of other functional blocks of the platform such as SerDes, and eTSEC, see the specific section of this document. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol Min f — G125 t — ...

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... V and DDR2 SDRAM Max Unit Notes μs — — — SYSCLKs 1 μs — — — SYSCLKs 1 — SYSCLKs 1 5 SYSCLKs 1 Unit Notes μs — μs — μs — μs — μs — (typ Freescale Semiconductor ...

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... DDR SDRAM component(s) when GV (typ Table 14. DDR SDRAM DC Electrical Characteristics for GV Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor . Symbol Min GV 1.7 DD 0.49 × REF – ...

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... MVREF must be able to supply up to 500 μA current. REF (typ) = 2.5 V (continued) DD Max Unit MV – 0.15 V REF μA 10 — mA — (typ Min Max Unit Notes — 0 GVDD/2, OUT REF Max Unit Note μA 500 1 Freescale Semiconductor Notes — 4 — — ...

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... MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t determined by the following equation the absolute value of t CISKEW 3. Maximum DDR1 frequency is 400 MHz. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol Min V — ...

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... MHz 2.40 t DDKHAX 533 MHz 1.48 400 MHz 1.95 333 MHz 2.40 t DDKHCS 533 MHz 1.48 400 MHz 1.95 333 MHz 2.40 can be calculated DISKEW Max Unit Notes — 7 — — — 7 — — — 7 — — Freescale Semiconductor ...

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... The data strobe should be centered inside of the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t symbol conventions described in note 1. 7. Maximum DDR1 frequency is 400 MHz MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 1 Symbol Min t ...

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... Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). MCK[n] MCK[n] MDQS MDQS MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE t MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 4. Timing Diagram for tDDKHMH Table 20 Freescale Semiconductor ...

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... MPC8568E. 7.1 DUART DC Electrical Characteristics Table 21 provides the DC electrical characteristics for the DUART interface. Table 21. DUART DC Electrical Characteristics Parameter High-level input voltage Low-level input voltage MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor t MCK t ,t DDKHAS DDKHCS t ,t DDKHAX ...

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... Value CCB clock/1,048,576 CCB clock/ sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are Min Max Unit μA — ±10 – 0.2 — V — 0.2 V Table 2 and Table 3. Unit baud baud — Freescale Semiconductor Notes 1,2 1,3 1,4 ...

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... Output low voltage (LV /TV = Min, IOL = 4.0 mA Input high voltage Input low voltage MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor and Table 24. The potential applied to the input of a GMII, MII, TBI, into a GMII receiver powered from a 2.5-V supply). OH Symbol Min LV 3 ...

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... Symbol Min Max LV /TV 2.37 2. 2. GND – 0.3 0. 1. –0.3 0. — –15 IL and TV symbols referenced Max Unit Notes μ μA — 3 Table 2 and Table 3. Unit Notes 0.3 V — — + 0.3 V — — μ μA — 3 Table 2 and Table 3. Freescale Semiconductor ...

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... RX_CLK peak-to-peak jitter Rise time RX_CLK (20%–80%) Fall time RX_CLK (80%–20%) RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Ethernet Interface and MII Management Table 25 and Table 26. ...

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... GTXH t GTKHDV t GTKHDX t GTXR t GTXF t G125R t G125F t t FITF FITR t FIRR t FIRF 1 Min Typ Max — 8.0 — 45 — 55 GTX 2.5 — — 0.5 — 5.0 2 — 1.0 2.0 2 — 1.0 2.0 — 1.0 2.0 — 1.0 2.0 Freescale Semiconductor Unit ...

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... Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise (20%-80%) MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor of 3.3 V ± 5%. DD Symbol t /t G125H (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... GMII (G) receive (RX) clock. For rise and fall times, the latter GRX = 50 Ω Figure 10. eTSEC AC Test Load t GRX t t GRXH GRXF t GRDXKH t GRDVKH Figure 11. GMII Receive AC Timing Diagram Min Typ Max — 1.0 2.0 symbolizes GMII GRDVKH Ω GRXR Freescale Semiconductor Unit ns clock ...

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... MII receive AC timing specifications. Table 30. MII Receive AC Timing Specifications At recommended operating conditions with L/TV Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor of 3.3 V ± 5 Symbol 2 t MTX ...

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... Figure 13. eTSEC AC Test Load t MRX t t MRXH MRXF Valid Data t MRDVKH Figure 14. MII Receive AC Timing Diagram Min Typ Max 10.0 — — 10.0 — — 1.0 — 4.0 1.0 — 4.0 symbolizes MII receive MRDVKH clock reference (K) MRX Ω MRXR t MRDXKL Freescale Semiconductor Unit ...

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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. Guaranteed by design. Figure 15 shows the TBI transmit AC timing diagram. GTX_CLK TCG[9:0] MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor of 3.3 V ± 5 Symbol t TTX ...

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... For example, symbolizes TBI TRDXKH clock reference TRX represents the TBI (T) TRX t TRXR Valid Data t TRDXKH t TRDXKH t TRDVKH Freescale Semiconductor Unit ...

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... RGMII and RTBI AC timing specifications. Table 34. RGMII and RTBI AC Timing Specifications At recommended operating conditions with LV Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) 3 Clock period duration MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol Min t 7.5 TRR t 40 TRRH t — ...

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... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev 2.5 V ± 5 RGTH RGT 5 t RGTR 5 t RGTF t G125R t G125F t /t G125H G125 represents the TBI (T) receive (RX) clock. Note RGT — 0.75 1.5 — 0.75 1.5 — 0.75 1.5 — 0.75 1 the lowest speed RGT Freescale Semiconductor % ...

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... Table 35. RMII Transmit AC Timing Specifications At recommended operating conditions with LV Parameter/Condition REF_CLK clock period REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] ...

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... Unit 1.0 — 10.0 (first two letters of functional block)(signal)(state) for outputs. For example, represents the MII(M) transmit MTX t RMTR Min Typ Max Unit 15.0 20.0 25 — — 250 1.0 — 2.0 1.0 — 2.0 4.0 — — Freescale Semiconductor ...

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... CRS_DV RX_ER 8.3 Ethernet Management Interface Electrical Characteristics The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor of 3.3 V ± 5 Symbol t RMRDX = 50 Ω ...

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... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 37. Symbol Min GND — — –600 IL symbols referenced in IN Symbol Min f — MDC Max Unit 3. 0 0.50 V — V 0.90 V μA 40 μA — Table 2 and Table 3. Max Unit Notes 2.5 MHz 2 Freescale Semiconductor ...

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... MDC to MDIO data valid t MDKHDV time – Max delay). Figure 22 shows the MII management AC timing diagram. Figure 22. MII Management Interface Timing Diagram MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol Min t 400 MDC t 32 MDCH ...

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... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Symbol Min Max –0.3 0 — ± 2.4 — — 0.4 OL symbol referenced in Table 2 IN Symbol Min V 1. –0 — 2 — OL symbol referenced in Table 3 Unit + 0 μ and Table Max Unit + 0 0.7 V μA 10 –15 — V 0.4 V and Table 3. Freescale Semiconductor ...

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... LBCR[AHD] parameter. 7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals Guaranteed by design. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Section 23.1, “Clock Ranges.” DD Symbol t LBKH/ ...

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... LSYNC_IN for PLL enabled or internal local bus clock for PLL = 2 2.5 V)—PLL Enabled Max Unit 150 ps — ns — ns — ns — ns — ns 3.0 ns 3.2 ns 3.2 ns 3.2 ns — ns — ns 2.6 ns 2.6 ns symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for is programmed LBOTOT Freescale Semiconductor Notes 2 — — ...

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... BV Table 43. Local Bus Timing Parameters—PLL Bypassed Parameter Local bus cycle time Local bus duty cycle MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor = 50 Ω Figure 23. Local Bus AC Test Load NOTE ...

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... LBKLOZ1 t — 0.2 LBKLOZ2 (First two letters of functional block)(signal)(state) (reference)(state) for outputs. For example, t symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for LBK clock reference ( high (H), with respect to the LBK Freescale Semiconductor Unit Notes ...

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... In PLL bypass mode, LCLK[n] is the inverted version of the internal clock with the delay of of the internal clock and are captured at falling edge of the internal clock with the exception of LGTA/LUPWAIT (which is captured on the rising edge of the internal clock). MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor t LBKHKT t LBKLOV1 t ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 27. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor t t LBKLOX1 LBKLOV1 t LBIVKH1 Local Bus ...

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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Enabled) MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...

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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 29. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV (PLL Bypass Mode) MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor t t LBKLOX1 LBKLOV1 t LBIVKH1 Local Bus ...

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... JTKLDX t TDO JTKLOX Min Max Unit 2.4 — — 0.5 — 0.4 2 0.3 DD -0.3 0.8 — ±10 uA Figure 31 through Figure 33. 1 Min Max Unit 0 33.3 MHz 30 — — — — 0 — — 25 — — 30 — Freescale Semiconductor Notes — — — ...

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... Figure 30. AC Test Load for the JTAG Interface Figure 31 provides the JTAG clock input timing diagram. JTAG External Clock Figure 31. JTAG Clock Input Timing Diagram Figure 32 provides the TRST timing diagram. TRST MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Table 3). 2 Symbol t JTKLDZ t TDO JTKLOZ (first two letters of functional block)(signal)(state) (reference)(state) for outputs ...

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... Figure 33. Boundary-Scan Timing Diagram 2 C interfaces. 2 Table 46 Electrical Characteristics of 3.3 V ± 5%. DD Symbol V t I2KHKL and JTDXKH Input Data Valid Output Data Valid 2 C interfaces of the MPC8568E. Min Max 0.7 × 0 0.3 × –0 0 – Freescale Semiconductor Unit Notes V — V — μA 3 ...

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... Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Electrical Characteristics (continued) of 3.3 V ± 5%. DD Symbol C is switched off ...

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... C Bus AC Timing Diagram (min) and V (max) levels (see Table 46 Symbol Min Max C — 400 b symbolizes I I2DVKH clock reference (K) going to the high I2C symbolizes I I2PVKH min of the SCL the SCL signal. I2CL Ω I2KHKL t I2PVKH P Freescale Semiconductor Unit pF for 2 C timing (I2 I2C S ...

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... PCI input clock. Table 49 Table 49. PCI AC Timing Specifications at 66 MHz Parameter SYSCLK to output valid Output hold from SYSCLK SYSCLK to output high impedance Input setup to SYSCLK Input hold from SYSCLK MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol Min V 0.5* –0 — ...

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... PCI 2.2 Local = 50 Ω Figure 36. PCI AC Test Load t PCIVKH Min Max Unit Notes 10 — clocks (first two letters of functional for outputs. For symbolizes PCRHFV of the signal in question Ω PCIXKH Freescale Semiconductor 8, 11 ...

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... A – B Volts. This is also referred as each signal wire’s Single-Ended Swing. 2. Differential Output Voltage, V The Differential Output Voltage (or Swing) of the transmitter, V the two complimentary output voltages negative. 3. Differential Input Voltage, V MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor CLK t PCKHOV t PCKHOZ Output (or Differential Output Swing): OD – ...

Page 62

... B| Volts. DIFFp DIFFp |(A – B)| Volts, which is twice of differential swing in DIFFp = 2*|V |. TX-DIFFp Differential Swing Differential Peak Voltage, V Differential Peak-Peak Voltage, V DIFFpp , is defined as the difference of the ID value can be either positive cm_out – – B| DIFFp = 2*V (not shown) DIFFp Freescale Semiconductor SD_TX ...

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... AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V DIFFp High-Speed Serial Interfaces (HSSI) ...

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... AC-coupled externally. For the best noise performance, the reference of the clock could be DC MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Ω Input Amp 50 Ω Figure 41 shows the SerDes reference clock input requirement Figure 42 shows the SerDes reference clock input Figure 43 shows Freescale Semiconductor ...

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... SD_REF_CLK Figure 42. Differential Reference Clock Input DC Requirements (External AC-Coupled) 400 mV SD_REF_CLK SD_REF_CLK Figure 43. Single-Ended Reference Clock Input DC Requirements MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Input Amplitude or Differential Peak < Input Amplitude or Differential Peak < < 8 SD_REF_CLK Input Amplitude High-Speed Serial Interfaces (HSSI) < ...

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... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

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... Clock Driver Clock Driver CLK_Out 10 nF Figure 45. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only) MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK Clock driver vendor dependent source termination resistor SD_REF_CLK 100 Ω ...

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... CLK_Out R1 Clock Driver Clock Driver CLK_Out R1 Figure 46. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only) MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK Figure 46 MPC8568E 50 Ω SerDes Refer. CLK Receiver 50 Ω Freescale Semiconductor ...

Page 69

... For better results, a source without significant unintended modulation should be used. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. ...

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... REFCLK cycle-to-cycle jitter. Difference in the period of any two REFCJ adjacent REFCLK cycles MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev SD_RXn SD_TXn 50 Ω 50 Ω SD_TXn SD_RXn 50 Ω Receiver 50 Ω Min Typical Max Units — 10 — ns — — 100 ps Freescale Semiconductor Notes 1 — ...

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... D+/D- TX Output TX-RISE TX-FALL Rise/Fall Time MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Min Nom Max Units 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 1. ...

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... TX specifications after leaving Electrical Idle 10 — — dB Measured over 50 MHz to 1.25 GHz. See Note 4 Comments = RMS(| |/2 – V TXD+ TXD- TX-CM- |/2 (avg) TX-D+ TX-D- V TX-CM-Idle-DC (During Electrical = |/2 [L0] (avg) TX-D+ TX- |/2 [Electrical (avg) TX-D+ TX- < TX-CM-DC- (avg) TX- (avg) TX- < TX-IDLE-D+ TX-IDLE-D- Freescale Semiconductor ) ...

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... The exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Min Nom Max ...

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... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev NOTE Min Nom Max Units 399.8 400 400. 0.175 — 1.200 V Comments Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations. See Note 2*|V – RX-DIFFp-p RX-D+ RX-D- See Note 2. Freescale Semiconductor ...

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... RX-HIGH-IMP-DC DC Input Impedance V Electrical Idle RX-IDLE-DET-DIFFp-p Detect Threshold T Unexpected RX-IDLE-DET-DIFF- Electrical Idle ENTERTIME Enter Detect Threshold Integration Time MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Min Nom Max Units 0.4 — — UI — — 0.3 UI — — 150 ...

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... Skew across all lanes on a Link. This includes variation in the length of SKP ordered set (for example, COM and one to five Symbols) at the RX as well as any delay differences arising from the interconnect itself. Figure 51 should be used Figure 50). If the specification ensures a jitter distribution in Freescale Semiconductor ...

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... D+ and D– not being exactly matched in length at the package pin boundary. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor NOTE Figure 51). Note that the series capacitors, CTX, are Figure ...

Page 78

... To ensure interoperability between drivers and receivers of different vendors and technologies, AC coupling at the receiver input must be used. 15.1 DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK For more information, see Section 13.2, “SerDes Reference Clocks.” MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

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... The peak-to-peak value of the differential transmitter output signal and the differential receiver input signal – B) Volts Volts Volts Figure 52. Differential Peak-Peak Voltage of Transmitter or Receiver MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Min Typical Max Units — 10(8) — — — ...

Page 80

... It is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps recommended that the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair not exceed 1.25 GB 2.50 GB and 3.125 GB. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Freescale Semiconductor ...

Page 81

... Total Jitter Multiple Output skew Unit Interval Table 56. Short Run Transmitter AC Timing Specifications—3.125 GBaud Characteristic Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Range Symbol Min Max V –0.40 2. 500 ...

Page 82

... Skew at the transmitter output between lanes of a multilane link ps +/–100 ppm Unit Notes Volts Voltage relative to COMMON of either signal comprising a differential pair mV p-p — UI p-p — UI p-p — ps Skew at the transmitter output between lanes of a multilane link ps +/– 100 ppm Freescale Semiconductor ...

Page 83

... Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized. V max DIFF V min DIFF 0 -VDIFF min -VDIFF max 0 Figure 53. Transmitter Output Compliance Mask MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Range Symbol Min Max V –0.40 2. 800 1600 DIFFPP J — ...

Page 84

... Unit Notes mV p-p Measured at receiver UI p-p Measured at receiver UI p-p Measured at receiver UI p-p Measured at receiver ns Skew at the receiver input between lanes of a multilane link — — ps +/– 100 ppm Figure 54. The sinusoidal jitter component Freescale Semiconductor ...

Page 85

... Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded region of is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Range Symbol Min ...

Page 86

... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Frequency (Table 61, Table 62, Table Figure 55 with the parameters specified in 1.875 MHz 20 MHz 63) when the eye pattern of the Table . The eye pattern of the Freescale Semiconductor ...

Page 87

... For the purpose of eye template measurements, the effects of a single-pole high pass filter with point at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor A B Time (UI) Figure 55 ...

Page 88

... Random jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in is then added to the signal and the test load is replaced by the receiver being tested. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev -12 . Freescale Semiconductor ...

Page 89

... Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least t operation Figure 56 provides the AC test load for the timers. Output MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol Condition –6 ...

Page 90

... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table 67. PIC DC Electrical Characteristics Symbol Condition V — — — 6 3 not relevant for those pins. OH Min Max Unit 2 -0.3 0.8 V μA ±10 — 0.5 V — 0 Symbol Min Unit PIWID Freescale Semiconductor ...

Page 91

... NMSI outputs internal timing (NI) for the time t NIKHOV the high state (H) until outputs (O) are valid (V). Figure 57 provides the AC test load for the SPI. Output MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Table 69. SPI DC Electrical Characteristics Symbol Condition –6.0 mA ...

Page 92

... Output low voltage Input high voltage MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table t NEIXKH t NEKHOV t NIIXKH t NIIVKH t NIKHOV Symbol Condition –2 3 — IH 72. Note that although the specifications Min Max Unit 2.4 — V — 0.5 V 2 Freescale Semiconductor ...

Page 93

... AC test load for the TDM/SI. Output Figure 61 represents the AC timing from reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol Condition V — ≤ V ≤ ...

Page 94

... Symbol Condition –8 8 — — ≤ V ≤ Table 74. Utopia AC Timing Specifications Symbol t t UEKHOV t t UEKHOX Min Max Unit 2.4 — — 0.5 2.0 OV +0.3 DD -0.3 0.8 μA — ± Min Max 0 8.0 UIKHOV 1 10.0 0 8.0 UIKHOX 1 10.0 Freescale Semiconductor Unit ...

Page 95

... Utopia timing with external clock. UtopiaCLK (input) t UEIVKH Input Signals: Utopia Output Signals: Utopia Figure 63. Utopia AC Timing (External Clock) Diagram MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Symbol t UIIVKH t UEIVKH t UIIXKH t UEIXKH (first two letters of functional block)(signal)(state) (first two letters of functional block)(reference)(state)(signal)(state Ω ...

Page 96

... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev UIIXKH t UIIVKH t UIKHOV t UIKHOX Symbol Condition –2 3 — — ≤ V ≤ Symbol t HIKHOV t HEKHOV Min Max Unit 2.4 — V — 0.5 V 2 -0.3 0.8 V μA — ± Min Max Unit 0 6 Freescale Semiconductor ...

Page 97

... HIKHOX high state (H) until outputs (O) are invalid (X). Figure 65 provides the AC test load. Output MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor HDLC, BISYNC, Transparent and Synchronous UART Symbol t HIKHOX t HEKHOX t HIIVKH ...

Page 98

... Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable Figure 67. AC Timing (Internal Clock) Diagram MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev Table t HEIXKH t HEKHOV t HEKHOX t HIIXKH t HIIVKH t HIKHOV t HIKHOX 76. Note that although the specifications Freescale Semiconductor ...

Page 99

... Ball diameter (typical) 22.2 Mechanical Dimensions of the MPC8568E FC-PBGA Figure 68 shows the top view, bottom and side view of the MPC8568E 1023 FC-PBGA package. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 33 mm × 1023 1 mm 2.23 – 2.75 mm 96.5% Sn 3.5% Ag ...

Page 100

... Package and Pinout 1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. All dimensions are symmetric across the package center lines, unless dimensioned otherwise. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 100 Figure 68. Top, Bottom, Side Views Freescale Semiconductor ...

Page 101

... This applies to both MPC8568E and MPC8568E. Note that for DUART1, there are two options. DUART0 is multiplexed with PCI Req/Grant pins. PCI_REQ[3] UART_CTS[0] PCI_REQ[4] UART_SIN[0] PCI_GNT[3] UART_RTS[0] PCI_GNT[4] UART_SOUT[0] For MPC8568E, GPIO is multiplexed with the TSEC2 interface: TSEC2_TXD[7:0] GPOUT[0:7] MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package and Pinout 101 ...

Page 102

... C11, E11, D9, A8, D12, A11, A9, C9 A21, E21, D18, B14, F11, A6, G5, A2, A10 Power Pin Type Notes Supply I/O OV — DD I/O OV — 5,9,35 DD I/O OV — I/O OV 2 — DD I/O OV — I I — DD I/O GV — DD I/O GV — — DD Freescale Semiconductor ...

Page 103

... LWE[3] LGPL0 LGPL1 LGPL2 MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number D21, G20, C17, D14, E10, C6, F4, C3, C10 C21, G21, C18, D15, F10, C7, F5, D3, B10 K7, H7, L7, J8, K8, L10, H9, K9, H10, G10, L6, K10, K11, H3, J11, J12 ...

Page 104

... AL13, AL11, AK13, AH13, AG11, AD13 AM13 AG13 AB13 AG12 AE11 AH11 AM12 Power Pin Type Notes Supply O BV 5 — — — — 5,9, — — — — — 2 5,9 DD I/O OV — — — — — — — — — DD Freescale Semiconductor ...

Page 105

... SD_TX[0:7] SD_TX[0:7] SD_PLL_TPD SD_RX_CLK SD_RX_FRM_CTL Reserved Reserved SD_REF_CLK SD_REF_CLK MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number AJ11 AC13 AL12 AC14, AD15, AB14, AH15, AD14, AH17, AE15, AC15 AM16 AJ15, AJ17, AF13, AK17, AH16, AG17 AL15 ...

Page 106

... Pin Type Notes Supply I/O OV 5, I/O OV — DD I/O OV — DD I/O OV — DD I/O OV — DD I/O TV — I/O TV — DD I/O OV — I/O OV — DD I/O TV — I/O TV — DD I/O OV — DD I/O OV 5,33 DD I/O OV — — — — 2,4 DD Freescale Semiconductor ...

Page 107

... SYSCLK TCK TDI TDO TMS TRST L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number Debug AL29 AM29 AK29, AJ29 AM28, AL28, AK27 AJ28 AF18 Clock AH20 AK22 JTAG AH18 ...

Page 108

... Ground for — — SerDes receiver Ground for — — SerDes transmitter Power for OVDD — PCI and other standards (3.3V) Power for LVDD — eTSEC1 and eTSEC2 (2.5V,3.3V) Power for QE TVDD — UCC1 and UCC2 Ethernet Interface (2,5V,3.3V) Freescale Semiconductor ...

Page 109

... AV DD_SRDS AGND_SRDS SENSEVDD MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number B2, B5, B8, B11, B17, B20, C14, D4, D7, D10, D16, D19, D22, E12, E15, F2, F6, F21, G9, G17, G18, H4, H11, H14, H20, J3, J6, J9, K13, L2, L5, L8, L11 B28, D27, D31, F25, F28, H27, H29, H31, K25, K27 ...

Page 110

... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 110 Package Pin Number M16 Analog Signals A24 K32 AA28 R30 Power Pin Type Notes Supply — — MVREF — Reference voltage signal for DDR I 200Ω to GND — I 100Ω to GND — O — 24 Freescale Semiconductor ...

Page 111

... Recommend a pull-up resistor (~1 K.) be placed on this pin to OV 29. The following pins must NOT be pulled down during power-on reset: HRESET_REQ, TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP, PA[5] MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number Ratio.” Section 23.3, “e500 Core PLL Ratio.” ...

Page 112

... AF29, AB18, AC18, AD18 AE18 AF23 AJ22 AF24 AD22 AE24 AK24 Power Pin Type Notes Supply through an 18.2-Ω precision DD Power Pin Type Notes Supply I/O OV — DD I/O OV — 5,9,35 DD I/O OV — I/O OV — I/O OV 2 Freescale Semiconductor ...

Page 113

... MCK[0:5] MCK[0:5] MODT[0:3] MDIC[0:1] LAD[0:31] LDP[0:3] LA[27] LA[28:31] MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number AG29, AJ27, AH29, AB17 AC17 AM26 AK23 AE21 AB19 DDR SDRAM Memory Interface B22, C22, E20, A19, C23, A22, A20, C20, G22, E22, ...

Page 114

... AD30, AG31, AL30, AF31, AD29, AK30, AG30, AF30 AD28 GPIO AC14, AD15, AB14, AH15, AD14, AH17, AE15, AC15 Power Pin Type Notes Supply O BVdd 8 O BVdd — 5,9, 5,8 5 — — — — 5,9, — — — — — 2 — DD Freescale Semiconductor ...

Page 115

... PA[0:4] PA[5] PA[6:31] PB[4:31] PC[0:31] PD[4:31] PE[5:7] PE[8:10] PE[11:19] MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number AM16, AJ15, AJ17, AF13, AK17, AH16, AG17, AL15 interface AE32 AD32 SerDes L30, M32, N30, P32, U30, V32, W30, Y32 ...

Page 116

... AH20 AK22 JTAG AH18 AH19 AJ18 AK19 AK20 Power Pin Type Notes Supply I/O OV — I/O OV — DD I/O TV — I/O TV — DD I/O OV — DD I/O OV 5,33 DD I/O OV — — — — 2 — 6,9,19 5,6 6,19, — — — Freescale Semiconductor ...

Page 117

... Table 79. MPC8567E Pinout Listing (continued) Signal L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL THERM0 THERM1 ASLEEP GND SCOREGND XGND MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number DFT AJ20 AJ19 AH31 AJ31 Thermal Management AB30 AB31 Power Management AK21 Power and Ground Signals ...

Page 118

... Power for VDD — Core (1.1) Core Power SCOREVDD — for SerDes transceivers (1.1V) Pad Power XVDD — for SerDes transceivers (1.1V) Power for — 26 local bus PLL (1.1V) Power for — 26 PCI PLL (1.1V) Power for — PLL (1.1V) Freescale Semiconductor ...

Page 119

... AV DD_PLAT AV DD_SRDS AGND_SRDS SENSEVDD SENSEVSS MVREF SD_IMP_CAL_RX SD_IMP_CAL_TX SD_PLL_TPA Reserved Reserved MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number AM24 AM20 R29 R31 M17 M16 Analog Signals A24 K32 AA28 R30 Reserved Pins AE17, AH12, AL13, AL11, AK13, AH13, AG11, ...

Page 120

... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 120 Package Pin Number Ratio.” Section 23.3, “e500 Core PLL Ratio.” /GND planes internally and may be used by the core power supply to improve tracking DD Ratio.” Power Pin Type Supply . DD Freescale Semiconductor Notes ...

Page 121

... Refer to Section 23.2, “CCB/SYSCLK PLL 2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Package Pin Number Termination.” Table 82 provides the clocking specifications for the local ...

Page 122

... MHz Min 25 Table 83. CCB Clock Ratio Binary Value of LA[28:31] Signals 16:1 1000 Reserved 1001 2:1 1010 3:1 1011 4:1 1100 Unit Notes Max 266 MHz 1, 2 Unit Notes Max 166 MHz 1 Table 83: CCB:SYSCLK Ratio 8:1 9:1 10:1 Reserved 12:1 Freescale Semiconductor ...

Page 123

... PA[0:4] Signals 0_0000 0_0001 0_0010 0_0011 0_0100 0_0101 0_0110 0_0111 MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Table 83. CCB Clock Ratio (continued) Binary Value of LA[28:31] Signals 5:1 1101 6:1 1110 Reserved 1111 Table 84. e500 Core to CCB Clock Ratio ...

Page 124

... SYSCLK (MHz) 33.33 41.66 66.66 83 Platform /CCB clock Frequency (MHz) 333 333 415 400 500 333 533 375 333 417 400 500 533 cfg_ce_pll[0: 100 111 133.33 166 333 333 400 500 400 445 533 500 Freescale Semiconductor ...

Page 125

... Thermal Management Information This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor × ( 527 MHz ...

Page 126

... Aavid Thermalloy, Advanced Thermal Solutions, Alpha Novatech, IERC, and MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 126 Figure 69. The heat sink should be attached to the printed-circuit FC-PBGA Package Heat Sink Heat Sink Clip Die 603-224-9988 781-769-2800 408-749-7601 818-842-7277 408-436-8770 Freescale Semiconductor ...

Page 127

... Internal Package Conduction Resistance For the packaging technology, shown in are as follows: • The die junction-to-case thermal resistance MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Unit Bump/Underfill W/(m × Figure 70. MPC8568E Thermal Model Table 87, the intrinsic internal conduction thermal resistance paths Figure 70 ...

Page 128

... Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 69). Therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 128 Radiation Convection Heat Sink Thermal Interface Material Die/Package Die Junction Package/Leads Radiation Convection Freescale Semiconductor ...

Page 129

... S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company th 18930 West 78 St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Contact Pressure (psi) ...

Page 130

... MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 130 888-246-9050 Section 23.2, “CCB/SYSCLK PLL Ratio.” Section 23.3, “e500 Core PLL , AV , and DD_LBIU DD_SRDS , and preferably these voltages will be derived directly from V DD Ratio.” respectively). The AV DD_CE DD DD Figure 73, one to each of the Freescale Semiconductor ...

Page 131

... DD utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 10 Ω 2.2 μF 2.2 μF Low ESL Surface Mount Capacitors GND 1.0 Ω ...

Page 132

... Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 132 , and LV planes, to enable quick recharging of the DD ensure and DD, VDD, Freescale Semiconductor ...

Page 133

... JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor System Design Information for normal ...

Page 134

... IC). Regardless of the numbering, the signal placement recommended in Figure 75 is common to all known emulators. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 134 allows the COP to independently assert HRESET or TRST, while adds many benefits—breakpoints, watchpoints, register and memory Figure 75; consequently, many different Freescale Semiconductor ...

Page 135

... Use a NOR gate with sufficient drive strength to drive two inputs. 25.9 Guidelines for High-Speed Interface Termination 25.9.1 Unused output Any of the outputs that are unused should be left unconnected. These signals are: • SD_TX[7:0] MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor SRESET HRESET HRESET 13 SRESET 11 TRST 4 10 Ω ...

Page 136

... PE[8:10]. Software must disable this mode through DEVDISR[SRIO] or DEVDISR[PCIE] accordingly during software initialization. 26 Ordering Information Contact your local Freescale sales office or regional marketing team for order information. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 136 DD_SRDS NOTE can be tied to GND, Freescale Semiconductor ...

Page 137

... Device Number 8568, 8567 Security Blank: No Security E: With Security Temperature Blank 105C C: -45(Ta) - 105C MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor Figure 76. MPC856Xxxxxxx ATWLYYWW MMMMM CCCCC FC-PBGA MPC 856x ANG J A Figure 77. MPC8568E Part Number Decoder Ordering Information ...

Page 138

... MPC8568E hardware specification. Rev Date Number 1 10/2010 In Table 78, “MPC8568E Pinout Listing,” and 49 to LGPL4. 0 05/2009 Initial public release. MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 138 Table 88. Document Revision History Substantive Change(s) Table 78, “MPC8568E Pinout Listing,” added footnote Freescale Semiconductor ...

Page 139

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...