KSZ8863FLLI Micrel Inc, KSZ8863FLLI Datasheet

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KSZ8863FLLI

Manufacturer Part Number
KSZ8863FLLI
Description
IC ETHERNET SWITCH 3PORT 48-LQFP
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8863FLLI

Controller Type
Ethernet Switch Controller
Interface
MII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Supplier Unconfirmed, Lead free / RoHS Compliant
Other names
576-3750

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General Description
The KSZ8863MLL/FLL/RLL are highly integrated 3-port
switch on a chip ICs in industry’s smallest footprint. They
are designed to enable a new generation of low port
count, cost-sensitive and power efficient 10/100Mbps
switch systems. Low power consumption, advanced
power management and sophisticated QoS features
(e.g., IPv6 priority classification support) make these
devices ideal for IPTV, IP-STB, VoIP, automotive and
industrial applications.
The KSZ8863 family is designed to support the GREEN
requirement in today’s switch systems. Advanced power
management schemes include software power down,
per port power down and the energy detect mode that
shuts downs the transceiver when a port is idle.
KSZ8863MLL/FLL/RLL also offer a by-pass mode, which
enables system-level power saving. In this mode, the
processor connected to the switch through the MII
interface can be shut down without impacting the normal
switch operation.
__________________________________________________________________________________________________________
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc
Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies.
August 2010
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (
408
The configurations provided by the KSZ8863 family
enables the flexibility to meet requirements of different
applications:
The device is available in RoHS-compliant 48-pin LQFP
package. Industrial-grade and Automotive-grade are
also available.
The datasheets and supporting documents can be found
at Micrel’s web site at: www.micrel.com.
) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
• KSZ8863MLL: Two 10/100BASE-T/TX transceivers
• KSZ8863RLL: Two 10/100BASE-T/TX transceivers
• KSZ8863FLL: One 100BASE-FX, one
Integrated 3-Port 10/100 Managed
and one MII interface.
and one RMII interface.
10/100BASE-T/TX transceivers and one MII
interface.
KSZ8863MLL/FLL/RLL
Switch with PHYs
Rev. 1.2
M9999-081810-1.2

Related parts for KSZ8863FLLI

KSZ8863FLLI Summary of contents

Page 1

... Functional Diagram LinkMD is a registered trademark of Micrel, Inc Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 ( August 2010 KSZ8863MLL/FLL/RLL ...

Page 2

Micrel, Inc. Features • Advanced Switch Features - IEEE 802.1q VLAN support for groups (full-range of VLAN IDs) - VLAN ID tag/untag options, per port basis - IEEE 802.1p/q tag insertion or removal on a per port ...

Page 3

... Ordering Information Part Number Junction Temperature Range KSZ8863MLL 0ºC to 70ºC KSZ8863MLLI –40ºC to +85ºC KSZ8863FLL 0ºC to 70ºC KSZ8863FLLI –40ºC to +85ºC KSZ8863RLL 0ºC to 70ºC KSZ8863RLLI –40ºC to +85ºC Revision History Revision Date Summary of Changes 1.0 ...

Page 4

Micrel, Inc. Contents Functional Diagram............................................................................................................................................................... 1 Applications........................................................................................................................................................................... 2 Pin Description and I/O Assignment ................................................................................................................................. 11 Pin Configuration ................................................................................................................................................................ 15 Functional Description ....................................................................................................................................................... 16 Functional Overview: Physical Layer Transceiver .......................................................................................................... 16 100BASE-TX Transmit ..................................................................................................................................................... 16 100BASE-TX Receive ...................................................................................................................................................... 16 PLL Clock ...

Page 5

Micrel, Inc. DiffServ-Based Priority .............................................................................................................................................. 33 Spanning Tree Support..................................................................................................................................................... 33 Rapid Spanning Tree Support .......................................................................................................................................... 34 Tail Tagging Mode ............................................................................................................................................................ 35 IGMP Support ................................................................................................................................................................... 36 IGMP Snooping ......................................................................................................................................................... 36 Multicast Address Insertion in the Static MAC Table ................................................................................................ 36 Port ...

Page 6

Micrel, Inc. Register 16 (0x10): Port 1 Control 0.......................................................................................................................... 55 Register 32 (0x20): Port 2 Control 0.......................................................................................................................... 55 Register 48 (0x30): Port 3 Control 0.......................................................................................................................... 55 Register 17 (0x11): Port 1 Control 1.......................................................................................................................... 56 Register 33 (0x21): Port 2 Control ...

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Micrel, Inc. Register 103 (0x67): TOS Priority Control Register 7 ............................................................................................... 67 Register 104 (0x68): TOS Priority Control Register 8 ............................................................................................... 67 Register 105 (0x69): TOS Priority Control Register 9 ............................................................................................... 68 Register 106 (0x6A): TOS Priority Control Register 10............................................................................................. ...

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Micrel, Inc. Register 177 (0xB1): TXQ Split for Q1 in Port 1........................................................................................................ 75 Register 178 (0xB2): TXQ Split for Q0 in Port 1........................................................................................................ 75 Register 179 (0xB3): TXQ Split for Q3 in Port 2........................................................................................................ 75 Register 180 (0xB4): TXQ Split ...

Page 9

Micrel, Inc. List of Figures 48-Pin LQFP (Top View) ..................................................................................................................................................... 15 Figure 1. Typical Straight Cable Connection ....................................................................................................................... 18 Figure 2. Typical Crossover Cable Connection ................................................................................................................... 19 Figure 3. Auto-Negotiation and Parallel Operation .............................................................................................................. 20 Figure 4. Destination Address Lookup ...

Page 10

Micrel, Inc. List of Tables Table 1. FX Signal Threshold............................................................................................................................................... 17 Table 2. MDI/MDI-X Pin Definitions ..................................................................................................................................... 17 Table 3. Internal Function Block Status ................................................................................................................................ 22 Table 4. MII Signals ............................................................................................................................................................. 27 Table 5. RMII Clock Setting .................................................................................................................................................. 28 Table ...

Page 11

Micrel, Inc. Pin Description and I/O Assignment Pin Number Pin Name 1 RXM1 2 RXP1 3 TXM1 4 TXP1 5 VDDA_3.3 6 ISET 7 VDDA_1.8 8 RXM2 9 RXP2 10 AGND 11 TXM2 12 TXP2 ...

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Micrel, Inc. Pin Number Pin Name 25 SMRXDV3 26 SMRXD33/ REFCLKO_3 27 SMRXD32 28 SMRXD31 29 SMRXD30 30 SMRXC3 31 GND 32 VDDC 33 SCOL3 34 SCRS3 35 INTRN 36 SCL_MDC 37 SDA_MDIO 38 SPIQ August 2010 (1) Type Description ...

Page 13

Micrel, Inc. Pin Number Pin Name 39 SPISN 40 VDDIO 41 GND 42 VDDCO 43 P1LED1 44 P1LED0 45 P2LED1 46 P2LED0 August 2010 (1) Type Description Strap option: Force flow control on port 1 (P1FFC always enable ...

Page 14

Micrel, Inc. Pin Number Pin Name 47 RSTN 48 FXSD1 Notes: 1. Speed : Low (100BASE-TX), High (10BASE-T) Full duplex : Low (full duplex), High (half duplex) Act : Toggle (transmit / receive activity) Link : Low (link), High (no ...

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Micrel, Inc. Pin Configuration August 2010 48-Pin LQFP (Top View) 15 KSZ8863MLL/FLL/RLL M9999-081810-1.2 ...

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Micrel, Inc. Functional Description The KSZ8863MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer 2 managed switch. The KSZ8863MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design managed ...

Page 17

Micrel, Inc. 100BASE-FX Signal Detection In 100BASE-FX operation, FXSD (fiber signal detect), input pin 48, is usually connected to the fiber transceiver SD (signal detect) output pin. The fiber signal threshold can be selected by register 192 bit 6 for ...

Page 18

Micrel, Inc. Straight Cable A straight cable connects an MDI device to an MDI-X device MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, ...

Page 19

Micrel, Inc. Crossover Cable A crossover cable connects an MDI device to another MDI device MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices). ...

Page 20

Micrel, Inc. Auto-Negotiation The KSZ8863MLL/FLL/RLL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3u specification. Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In auto- negotiation, link partners ...

Page 21

Micrel, Inc. ® LinkMD Cable Diagnostics KSZ8863MLL/FLL/RLL supports the LinkMD the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismatches. ® LinkMD works by sending a pulse of known amplitude and duration down the ...

Page 22

Micrel, Inc. Table 3 indicates all internal function blocks status under four different power management operation modes. KSZ8863MLL/FLL/RLL Function Blocks Normal Mode Internal PLL Clock Enabled Tx/Rx PHY Enabled MAC Enabled Host Interface Enabled Normal Operation Mode This is the ...

Page 23

Micrel, Inc. Functional Overview: MAC and Switch Address Lookup The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address table plus switching information. The KSZ8863MLL/FLL/RLL is guaranteed to learn 1K addresses and distinguishes ...

Page 24

Micrel, Inc. Figure 4. Destination Address Lookup Flow Chart, Stage 1 August 2010 24 KSZ8863MLL/FLL/RLL M9999-081810-1.2 ...

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Micrel, Inc. Figure 5. Destination Address Resolution Flow Chart, Stage 2 The KSZ8863MLL/FLL/RLL will not forward the following packets: 1. Error packets These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. IEEE802.3x ...

Page 26

Micrel, Inc. Switching Engine The KSZ8863MLL/FLL/RLL features a high-performance switching engine to move data to and from the MACs’ packet buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency. The switching engine has ...

Page 27

Micrel, Inc. To ensure no packet loss in 10 BASE-T or 100 BASE-TX half duplex modes, the user must enable the following: 4. Aggressive back-off (register 3 (0x03), bit [0 excessive collision drop (register 4 (0x04), bit [3]) ...

Page 28

Micrel, Inc. The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid ...

Page 29

Micrel, Inc. The RMII provided by the KSZ8863RLL is connected to the device’s third MAC. It complies with the RMII Specification. The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on ...

Page 30

Micrel, Inc. MII Management (MIIM) Interface The KSZ8863MLL/FLL/RLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8863MLL/FLL/RLL. An external ...

Page 31

Micrel, Inc. Serial Management Interface (SMI) The SMI is the KSZ8863MLL/FLL/RLL non-standard MIIM interface that provides access to all KSZ8863MLL/FLL/RLL configuration registers. This interface allows an external device to completely monitor and control the states of the KSZ8863MLL/FLL/RLL. The SMI ...

Page 32

Micrel, Inc. DA found in Static Use FID flag? MAC Table? No Don’t care No Don’t care Yes 0 Yes 1 Yes 1 Yes 1 FID+SA found in Dynamic MAC Table? No Yes Advanced VLAN features, such as “Ingress VLAN ...

Page 33

Micrel, Inc. 802.1p-based priority is enabled by bit [5] of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. The KSZ8863MLL/FLL/RLL provides the option to insert or remove the priority tagged frame's header at each individual egress ...

Page 34

Micrel, Inc. Disable State Port Setting The port should “transmit not forward or enable = 0, receive any receive enable packets. Learning = 0, learning is disabled. disable =1” Blocking State Port Setting Only packets to “transmit the processor are ...

Page 35

Micrel, Inc. Ports in Forwarding states fully participate in both data forwarding and MAC learning. Forwarding state: packets are forwarded and received normally. Learning is enabled. Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.” ...

Page 36

Micrel, Inc. IGMP Support For Internet Group Management Protocol (IGMP) support in layer 2, the KSZ8863MLL/FLL/RLL provides two components: IGMP Snooping The KSZ8863MLL/FLL/RLL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are identified ...

Page 37

Micrel, Inc. To reduce congestion good practice to make sure the egress bandwidth exceeds the ingress bandwidth. Unicast MAC Address Filtering The unicast MAC address filtering function works in conjunction with the static MAC address table. First, ...

Page 38

Micrel, Inc. I2C Slave Serial Bus Configuration In managed mode, the KSZ8863MLL/FLL/RLL can be configured device (external controller/CPU) has complete programming access to the KSZ8863MLL/FLL/RLL’s 198 registers. Programming access includes the Global Registers, Port Registers, Advanced Control ...

Page 39

Micrel, Inc. The KSZ8863MLL/FLL/RLL is capable of supporting a SPI bus. The following is a sample procedure for programming the KSZ8863MLL/FLL/RLL using the SPI bus the board level, connect the KSZ8863MLL/FLL/RLL pins as follows: KSZ8863MLL/FLL/RLL Pin # 39 ...

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Micrel, Inc. August 2010 Figure 12. SPI Multiple Write Figure 13. SPI Multiple Read 40 KSZ8863MLL/FLL/RLL M9999-081810-1.2 ...

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Micrel, Inc. Loopback Support The KSZ8863MLL/FLL/RLL provides loopback support for remote diagnostic of failure. In loopback mode, the speed at both PHY ports needs to be set to 100BASE-TX. Two types of loopback are supported: Far-end Loopback and Near-end (Remote) ...

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Micrel, Inc. Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2.of the KSZ8863MLL/FLL/RLL. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, ...

Page 43

Micrel, Inc. MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I also be used to access some of these registers. The latter three interfaces use a different ...

Page 44

Micrel, Inc. PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control Bit Name R/W 15 Soft reset RO 14 Loopback R/W 13 Force 100 R/W ...

Page 45

Micrel, Inc. PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status Bit Name R capable RO 14 100 Full RO capable 13 100 ...

Page 46

Micrel, Inc. PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability Bit Name R/W 15 Next page RO 14 Reserved RO 13 Remote fault RO ...

Page 47

Micrel, Inc. PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): Not support PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status Bit Name R/W 15 Vct_enable R/W (SC) 14-13 Vct_result RO 12 Vct 10M Short RO 11-9 ...

Page 48

Micrel, Inc. Memory Map (8-bit Registers) Global Registers Register (Decimal) Register (Hex) 0-1 0x00-0x01 2-15 0x02-0x0F Port Registers Register (Decimal) Register (Hex) 16-29 0x10-0x1D 30-31 0x1E-0x1F 32-45 0x20-0x2D 46-47 0x2E-0x2F 48-57 0x30-0x39 58-62 0x3A-0x3E 63 0x3F 64-95 0x40-0x5F Advanced Control ...

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Micrel, Inc. Register Description Global Registers (Registers 0 – 15) Register 0 (0x00): Chip ID0 Bit Name R/W 7-0 Family ID RO Register 1 (0x01): Chip ID1 / Start Switch Bit Name R/W 7-4 Chip ID RO 3-1 Revision ID ...

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Micrel, Inc. Register 3 (0x03): Global Control 1 Bit Name R/W 7 Pass All R/W Frames 6 Port 3 Tail Tag R/W Mode Enable 5 IEEE 802.3x R/W Transmit Direction Flow Control Enable 4 IEEE 802.3x R/W Receive Direction Flow ...

Page 51

Micrel, Inc. Bit Name R/W 2 Huge Packet R/W Support 1 Legal R/W Maximum Packet Size Check Enable 0 Reserved R/W Register 5 (0x05): Global Control 3 Bit Name R/W 7 802.1Q VLAN R/W Enable 6 IGMP Snoop R/W Enable ...

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Micrel, Inc. Register 6 (0x06): Global Control 4 Bit Name R/W 7 Reserved RO 6 Switch MII Half R/W Duplex Mode 5 Switch MII R/W Flow Control Enable 4 Switch MII R/W 10BT 3 Null VID R/W Replacement 2-0 Broadcast ...

Page 53

Micrel, Inc. Register 8 (0x08): Global Control 6 Bit Name R/W 7-0 Factory RO Testing Register 9 (0x09): Global Control 7 Bit Name R/W 7-0 Factory RO Testing Register 10 (0x0A): Global Control 8 Bit Name R/W 7-0 Factory RO ...

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Micrel, Inc. Register 14 (0x0E): Global Control 12 Bit Name R/W Description 7 Unknown R/W Send packets with unknown destination MAC addresses to specified port(s) in bits [2:0] of this register. Packet Default 0 = disable Port 1 = enable ...

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Micrel, Inc. Port Registers (Registers 16 – 95) The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port ...

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Micrel, Inc. Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Bit Name R/W Description 7 Sniffer Port R Port is designated as sniffer port and ...

Page 57

Micrel, Inc. Bit Name R/W 3 Back R/W Pressure Enable 2 Transmit R/W Enable 1 Receive R/W Enable 0 Learning R/W Disable Note: Bits [2:0] are used for spanning tree support. Register 19 (0x13): Port 1 Control 3 Register 35 ...

Page 58

Micrel, Inc. Bit Name R/W 5 Self-address R/W filtering enable MACA2 (not for 0x35) 4 Drop Ingress R/W Tagged Frame 3-2 Limit Mode R/W 1 Count IFG R/W 0 Count Pre R/W Register 22[6:0] (0x16): Port 1 Q0 ingress data ...

Page 59

Micrel, Inc. Register 23[6:0] (0x17): Port 1 Q1 ingress data rate limit Register 39[6:0] (0x27): Port 2 Q1 ingress data rate limit Register 55[6:0] (0x37): Port 3 Q1 ingress data rate limit Bit Name R/W 7 Reserved R/W 6-0 Q1 ...

Page 60

Micrel, Inc. Data Rate Limit for ingress or egress 64 Kbps 128 Kbps 192 Kbps 256 Kbps 320 Kbps 384 Kbps 448 Kbps 512 Kbps 576 Kbps 640 Kbps 704 Kbps 768 Kbps 832 Kbps 896 Kbps 960 Kbps September ...

Page 61

Micrel, Inc. Register 26 (0x1A): Port 1 PHY Special Control/Status Register 42 (0x2A): Port 2 PHY Special Control/Status Register 58 (0x3A): Reserved, not applied to port 3 Bit Name R/W 7 Vct 10M Short RO 6-5 Vct_result RO 4 Vct_en ...

Page 62

Micrel, Inc. Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Reserved, not applied to port 3 Bit Name R/W 7 Auto R/W Negotiation Enable 6 Force Speed R/W 5 Force Duplex ...

Page 63

Micrel, Inc. Bit Name R/W 5 Restart AN R/W 4 Disable Far- R/W end Fault 3 Power Down R/W 2 Disable Auto R/W MDI/MDI-X 1 Force MDI R/W 0 Loopback R/W Register 30 (0x1E): Port 1 Status 0 Register 46 ...

Page 64

Micrel, Inc. Register 31 (0x1F): Port 1 Status 1 Register 47 (0x2F): Port 2 Status 1 Register 63 (0x3F): Port 3 Status 1 Bit Name R/W 7 Hp_mdix R/W 6 Reserved RO 5 Polrvs RO 4 Transmit Flow RO Control ...

Page 65

Micrel, Inc. Advanced Control Registers (Registers 96-198) The IPv4/IPv6 TOS Priority Control Registers implement a fully decoded, 128-bit DSCP (Differentiated Services Code Point) register set that is used to determine priority from the ToS (Type of Service) field in the ...

Page 66

Micrel, Inc. Register 99 (0x63): TOS Priority Control Register 3 Bit Name R/W 7-6 DSCP[31:30] R/W 5-4 DSCP[29:28] R/W 3-2 DSCP[27:26] R/W 1-0 DSCP[25:24] R/W Register 100 (0x64): TOS Priority Control Register 4 Bit Name R/W 7-6 DSCP[39:38] R/W 5-4 ...

Page 67

Micrel, Inc. Register 102 (0x66): TOS Priority Control Register 6 Bit Name R/W 7-6 DSCP[55:54] R/W 5-4 DSCP[53:52] R/W 3-2 DSCP[51:50] R/W 1-0 DSCP[49:48] R/W Register 103 (0x67): TOS Priority Control Register 7 Bit Name R/W 7-6 DSCP[63:62] R/W 5-4 ...

Page 68

Micrel, Inc. Register 105 (0x69): TOS Priority Control Register 9 Bit Name R/W 7-6 DSCP[79:78] R/W 5-4 DSCP[77:76] R/W 3-2 DSCP[75:74] R/W 1-0 DSCP[73:72] R/W Register 106 (0x6A): TOS Priority Control Register 10 Bit Name R/W 7-6 DSCP[87:86] R/W 5-4 ...

Page 69

Micrel, Inc. Register 108 (0x6C): TOS Priority Control Register 12 Bit Name R/W 7-6 DSCP[103:102] R/W 5-4 DSCP[101:100] R/W 3-2 DSCP[99:98] R/W 1-0 DSCP[97:96] R/W Register 109 (0x6D): TOS Priority Control Register 13 Bit Name R/W 7-6 DSCP[111:110] R/W 5-4 ...

Page 70

Micrel, Inc. Register 111 (0x6F): TOS Priority Control Register 15 Bit Name R/W 7-6 DSCP[127:126] R/W 5-4 DSCP[125:124] R/W 3-2 DSCP[123:122] R/W 1-0 DSCP[121:120] R/W Registers 112 to 117 Registers 112 to 117 contain the switch engine’s MAC address. This ...

Page 71

Micrel, Inc. Registers 118 to 120 Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be used to pass user defined control and status information between the KSZ8863 and the external processor. ...

Page 72

Micrel, Inc. Register 124 (0x7C): Indirect Data Register 7 Bit Name R/W 7-0 Indirect Data R/W [63:56] Register 125 (0x7D): Indirect Data Register 6 Bit Name R/W 7-0 Indirect Data R/W [55:48] Register 126 (0x7E): Indirect Data Register 5 Bit ...

Page 73

Micrel, Inc. Register 154[6:0] (0x9A): Port 1 Q0 Egress data rate limit Register 158[6:0] (0x9E): Port 2 Q0 Egress data rate limit Register 162[6:0] (0xA2): Port 3 Q0 Egress data rate limit Bit Name R/W 7 Egress Rate R/W Limit ...

Page 74

Micrel, Inc. Register 166 (0xA6): KSZ8863 mode indicator Bit Name RO 7-0 KSZ8863 RO Mode Indicator Register 167 (0xA7): High Priority Packet Buffer Reserved for Q3 Bit Name RW 7-0 Reserved RO Register 168 (0xA8): High Priority Packet Buffer Reserved ...

Page 75

Micrel, Inc. Register 173 (0xAD): PM Usage Flow Control Select Mode 3 Bit Name R/W 7-6 Reserved RO 5-0 Reserved RO Register 174 (0xAE): PM Usage Flow Control Select Mode 4 Bit Name R/W 7-4 Reserved RO 3-0 Reserved RO ...

Page 76

Micrel, Inc. Register 180 (0xB4): TXQ Split for Q2 in Port 2 Bit Name R/W 7 Reserved RO 6:0 Reserved RO Register 181 (0xB5): TXQ Split for Q1 in Port 2 Bit Name R/W 7 Reserved RO 6:0 Reserved RO ...

Page 77

Micrel, Inc. Register 187 (0xBB): Interrupt enable register Bit Name R/W 7-0 Interrupt R/W Enable Register Register 188 (0xBC): Link Change Interrupt Bit Name R Link R/W Change (LC) Interrupt 6-3 Reserved R Link ...

Page 78

Micrel, Inc. Register 194 (0xC2): Insert SRC PVID Bit Name R/W 7-6 Reserved RO 5 Insert SRC R/W port 1 PVID at Port 2 4 Insert SRC R/W port 1 PVID at Port 3 3 Insert SRC R/W port 2 ...

Page 79

Micrel, Inc. Bit Name R/W 1-0 Power R/W Management Mode Register 196(0xC4): Sleep Mode Bit Name R/W 7-0 Sleep Mode R/W Register 198 (0xC6): Forward Invalid VID Frame and Host Mode Bit Name R/W 7 Reserved RO 6-4 Forward Invid ...

Page 80

Micrel, Inc. Static MAC Address Table The KSZ8863 supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look up, the KSZ8863 searches both tables to make a packet forwarding decision. In response ...

Page 81

Micrel, Inc. 2. Static Address Table Write (Write the 8 Write to reg. 124 (0x7C), static table bits [57:56] Write to reg. 125 (0x7D), static table bits [55:48] Write to reg. 126 (0x7E), static table bits [47:40] Write to reg. ...

Page 82

Micrel, Inc. VLAN Table The KSZ8863 uses the VLAN table to perform look ups. If 802.1Q VLAN mode is enabled (register 5, bit 7 = 1), this table will be used to retrieve the VLAN information that is associated with ...

Page 83

Micrel, Inc. Dynamic MAC Address Table The KSZ8863 maintains the dynamic MAC address table. Read access is allowed only. Bit Name 71 Data Not Ready 70-67 Reserved 66 MAC Empty 65- Valid Entries 55-54 Time Stamp 53-52 Source ...

Page 84

Micrel, Inc. MIB (Management Information Base) Counters The KSZ8863 provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped ...

Page 85

Micrel, Inc. Offset Counter Name 0x16 TxLateCollision 0x17 TxPausePkts 0x18 TxBroadcastPkts 0x19 TxMulticastPkts 0x1A TxUnicastPkts 0x1B TxDeferred 0x1C TxTotalCollision 0x1D TxExcessiveCollision 0x1E TxSingleCollision 0x1F TxMultipleCollision Table 19. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets Bit Name 30-16 Reserved ...

Page 86

Micrel, Inc. “All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters are shown in the following table: Offset Counter Name 0x100 Port1 TX Drop Packets 0x101 Port2 TX Drop Packets 0x102 ...

Page 87

Micrel, Inc. Absolute Maximum Ratings Supply Voltage (VDDA_1.8, VDDC) ................................. –0.5V to 2.4V (VDDA_3.3V, VDDIO).............................. –0.5V to 4.0V Input Voltage ................................................. –0.5V to 4.0V Output Voltage .............................................. –0.5V to 4.0V Lead Temperature (soldering, 10sec.) ....................... 270°C Storage Temperature (T ) ...

Page 88

Micrel, Inc. Symbol Parameter T /T Rise/Fall Time r f Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot Output Jitter 10BASE-T Receive V Squelch Threshold SQ 10BASE-T Transmit (measured differentially after 1:1 transformer) V Peak Differential Output Voltage P Output Jitter ...

Page 89

Micrel, Inc. Timing Specifications EEPROM Timing Symbols t cyc1 ov1 September 2009 Figure 16. EEPROM Interface Input Timing Diagram Figure 17. EEPROM Interface Output Timing Diagram Parameters Clock cycle Setup time Hold time Output valid ...

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Micrel, Inc. MII Timing Figure 18. MAC Mode MII Timing – Data Received from MII Figure 19. MAC Mode MII Timing – Data Transmitted to MII Symbol September 2009 10Base-T/100Base-TX Parameter Min Clock Cycle CYC3 Set-Up ...

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Micrel, Inc. Symbol t CYC4 OV4 September 2009 Figure 20. PHY Mode MII Timing – Data Received from MII Figure 21. PHY Mode MII Timing – Data Transmitted to MII 10BaseT/100BaseT Parameter Min Clock Cycle ...

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Micrel, Inc. RMII Timing Symbols tcyc t1 t2 tod September 2009 Figure 22. RMII Timing – Data Received from RMII Figure 23. RMII Timing – Data Transmitted to RMII Parameters Min Clock cycle Setup time 4 Hold time 2 Output ...

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Micrel, Inc Slave Mode Timing September 2009 Figure 24. I2C Input Timing Figure 25. I2C Start Bit Timing Figure 26. I2C Stop Bit Timing Figure 27. I2C Output Timing 93 KSZ8863MLL/FLL/RLL M9999-091009-1.1 ...

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Micrel, Inc. Symbols Parameters t Clock cycle CYC t Setup time S t Hold time H t Start bit setup time TBS t Start bit hold time TBH t Stop bit setup time SBS t Stop bit hold time SBH ...

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Micrel, Inc. SPI Timing Symbols CHSL t SLCH t CHSH t SHCH t SHSL t DVCH t CHDX t CLCH t CHCL t DLDH t DHDL September 2009 Figure 28. SPI Input Timing Parameters Clock frequency SPISN ...

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Micrel, Inc. Symbols CLQX t CLQV QLQH t QHQL t SHQZ September 2009 Figure 29. SPI Output Timing Parameters Clock frequency SPIQ hold time Clock low to SPIQ valid Clock high time ...

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Micrel, Inc. Auto-Negotiation Timing Symbols Parameters tBTB FLP burst to FLP burst tFLPW FLP burst width tPW Clock/Data pulse width tCTD Clock pulse to Data pulse tCTC Clock pulse to Clock pulse Number of Clock/Data pulse per burst September 2009 ...

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Micrel, Inc. MDC/MDIO Timing Timing Parameter Description t MDC period P t MDIO (PHY input) setup to rising edge of MDC 1MD1 t MDIO (PHY input) hold from rising edge of MDC MD2 t MDIO (PHY output) delay from rising ...

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Micrel, Inc. Reset Timing The KSZ8863MLL/FLL/RLL reset timing requirement is summarized in the following figure and table. Symbols Parameters Stable supply voltages to reset High t sr Configuration setup time Configuration hold time ch Reset to strap-in ...

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Micrel, Inc. Reset Circuit The reset circuit in Figure 33 is recommended for powering up the KSZ8863MLL/FLL/RLL if reset is triggered only by the power supply. The reset circuit in Figure 34 is recommended for applications where reset is driven ...

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Micrel, Inc. Selection of Isolation Transformers An 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Turns ratio Open-circuit ...

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Micrel, Inc. Package Information MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information ...

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