HFIXF1110CC.B3-998844 Cortina Systems Inc, HFIXF1110CC.B3-998844 Datasheet
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Cortina Systems Ethernet Media Access Controller Datasheet ® The Cortina Systems IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller (IXF1110 MAC 10-port Ethernet Media Access Controller (MAC) that supports IEEE 802.3 1000 Mbps applications. The device supports a ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Contents 1.0 Introduction.................................................................................................................................. 14 1.1 What You Will Find in This Document ................................................................................ 14 1.2 Related Documents ............................................................................................................ 14 2.0 General Description .................................................................................................................... 15 3.0 Ball Assignments and Ball List Tables...................................................................................... ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2.2.10 MaxBurst2.............................................................................................. 62 5.2.3 Dynamic Phase Alignment Training Sequence (Data Path De-skew) ................... 62 5.2.3.1 Training at Start-up ................................................................................ 62 5.2.3.2 Periodic Training .................................................................................... 62 5.2.3.3 Training in a Practical Implementation................................................... ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.7.5 Boundary Scan Register........................................................................................ 89 5.7.6 Bypass Register..................................................................................................... 89 5.8 Clocks ................................................................................................................................. 90 5.8.1 System Interface Reference Clocks ...................................................................... 90 5.8.1.1 CLK125 .................................................................................................. 90 5.8.1.2 CLK50 .................................................................................................... 90 5.8.2 SPI4-2 Receive ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 8.5 Memory Map..................................................................................................................... 118 8.5.1 MAC Control Registers ........................................................................................ 125 8.5.2 MAC RX Statistics Register Overview ................................................................. 133 8.5.3 MAC TX Statistics Register Overview ................................................................. 136 8.5.4 Global Status and Configuration ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figures 1 IXF1110 MAC Block Diagram........................................................................................................ 15 2 IXF1110 MAC System Block Diagram........................................................................................... 16 3 552-Ball CBGA Assignments (Top View) ...................................................................................... 17 4 Interface Diagram .......................................................................................................................... 19 5 Packet Buffering FIFO ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Tables 1 SPI4-2 Interface Signal Descriptions............................................................................................. 20 2 SerDes Interface Signal Descriptions............................................................................................ 22 3 CPU Interface Signal Descriptions ................................................................................................ 23 4 Pause Control Interface Signal Descriptions ................................................................................. 24 5 Optical Module ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 51 MAC Control Register Map.......................................................................................................... 118 52 MAC RX Statistics Register Map................................................................................................. 119 53 MAC TX Statistics Register Map ................................................................................................. 120 54 Global Status and Configuration Register Map ........................................................................... 121 55 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 102 SPI4-2 RX Training ($ 0x701) ..................................................................................................... 163 103 SPI4-2 RX Calendar ($ 0x702).................................................................................................... 164 104 SPI4-2 TX Synchronization ($ 0x703) ......................................................................................... 165 105 SerDes Tx Driver Power Level Ports 0-6 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Revision History 2 Updated Section 5.4.4. Protocol Specifics, on page Updated Figure 29, Analog Power Supply Filter Network, on page Updated Table 36, 2.5 V CMOS and 3.3 V ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Changed product ordering number to reflect B2 [HFIXF1110CC.B2: 860817]. Modified Table 11 “Power Supply Signal Descriptions” [changed AVDD to AVDD1P8_1/2 and AVDD2 to AVDD2P5_1/2]. Added note under Section 5.1.2.1, “Padding of ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Added Section 5.5.4.1 “Transmitter Programmable Driver-Power Added Table 21 “IXF1110 SerDes Driver TX Power Levels”. Changed Gigabit Interface Converter section to Modified Section 5.4.3.2.1, “MOD_DEF_9:0”. Modified Section 5.6.3.2.2, “TX_FAULT_9:0”. Modified Section ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 1.0 Introduction This datasheet describes the functionality and operation of the Cortina Systems 10-Port 1000 Mbps Ethernet Media Access Controller (IXF1110 MAC). 1.1 What You Will Find in This Document This ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 2.0 General Description The IXF1110 MAC is a 10-port 1000 Mbps Ethernet Media Access Controller (MAC). The 10 Gigabit interface to the network processor is supported through a System Packet Interface ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 2 IXF1110 MAC System Block Diagram LED Serial-to-Parallel Converter ® Cortina Systems IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Forwarding Engine Network Processor SPI4-2 LED Serial IXF1110 Interface SerDes/Optical ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 3.0 Ball Assignments and Ball List Tables Figure 3 illustrates the 552-Ball CBGA assignments. tables in alphanumeric order by signal name and ball location under Tables, on page 30. Figure 3 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.0 Ball Assignments and Signal Descriptions 4.1 Naming Conventions 4.1.1 Signal Name Conventions Signal names begin with a Signal Mnemonic, and can also contain one or more of the following designations: ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 4 Interface Diagram TDAT[15:0]_P/N SPI4-2 RDAT[15:0]_P/N Interface JTAG Interface Pause Control TXPAUSEADD[3:0] Interface UPX_DATA[31:0] UPX_ADD[10:0] CPU Interface ® Cortina Systems IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller TDCLK_P/N TCTL_P/N ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 1 SPI4-2 Interface Signal Descriptions (Sheet Signal Name TDAT15_P, TDAT15_N TDAT14_P, TDAT14_N TDAT13_P, TDAT13_N TDAT12_P, TDAT12_N TDAT11_P, TDAT11_N TDAT10_P, TDAT10_N TDAT9_P, TDAT9_N TDAT8_P, TDAT8_N TDAT7_P, TDAT7_N TDAT6_P, ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 1 SPI4-2 Interface Signal Descriptions (Sheet Signal Name RDAT15_P, RDAT15_N RDAT14_P, RDAT14_N RDAT13_P, RDAT13_N RDAT12_P, RDAT12_N RDAT11_P, RDAT11_N RDAT10_P, RDAT10_N RDAT9_P, RDAT9_N RDAT8_P, RDAT8_N RDAT7_P, RDAT7_N RDAT6_P, ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 2 SerDes Interface Signal Descriptions Signal Name TX_P_0, TX_N_0 TX_P_1, TX_N_1 TX_P_2, TX_N_2 TX_P_3, TX_N_3 TX_P_4, TX_N_4 TX_P_5, TX_N_5 TX_P_6, TX_N_6 TX_P_7, TX_N_7 TX_P_8, TX_N_8 TX_P_9, TX_N_9 RX_P_0, RX_N_0 RX_P_1, ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 3 CPU Interface Signal Descriptions (Sheet Signal Name UPX_ADD10 UPX_ADD9 UPX_ADD8 UPX_ADD7 UPX_ADD6 UPX_ADD5 UPX_ADD4 UPX_ADD3 UPX_ADD2 UPX_ADD1 UPX_ADD0 UPX_CS_L UPX_DATA31 UPX_DATA30 UPX_DATA29 UPX_DATA28 UPX_DATA27 UPX_DATA26 UPX_DATA25 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 3 CPU Interface Signal Descriptions (Sheet Signal Name UPX_WR_L UPX_RD_L UPX_RDY_L 1. This I/O meets the 2.5 V CMOS specification only during boundary scan mode. Table 4 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 5 Optical Module Interface Signal Descriptions (Sheet Signal Name TX_FAULT_0 TX_FAULT_1 TX_FAULT_2 TX_FAULT_3 TX_FAULT_4 TX_FAULT_5 TX_FAULT_6 TX_FAULT_7 TX_FAULT_8 TX_FAULT_9 RX_LOS_0 RX_LOS_1 RX_LOS_2 RX_LOS_3 RX_LOS_4 RX_LOS_5 RX_LOS_6 RX_LOS_7 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 5 Optical Module Interface Signal Descriptions (Sheet Signal Name RX_LOS_INT MOD_DEF_INT 2 I C_CLK 2 I C_DATA_0 2 I C_DATA_1 2 I C_DATA_2 2 I C_DATA_3 2 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 7 JTAG Interface Signal Descriptions (Sheet Signal Name TDI TRST_L TDO Table 8 System Interface Signal Descriptions Signal Name CLK125 CLK50 SYS_RES_L Table 9 Power Supply Signal ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 9 Power Supply Signal Descriptions (Sheet Signal Name VDD VDD2 GND ® Cortina Systems IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type D6 D10 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 10 Unused Balls/Reserved Signal Name NC No Ball No Pad ® Cortina Systems IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller Ball Designator Type A5 A6 C10 C15 G7 G8 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 4.3 Ball List Tables Ball list tables are provided in alphanumeric order by signal name location order (Table Note: Cortina recommends that all unconnected balls be tied to their inactive states ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Signal ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Signal RX_LOS_9 RX_LOS_INT RX_N_0 RX_N_1 RX_N_2 RX_N_3 RX_N_4 RX_N_5 RX_N_6 RX_N_7 RX_N_8 RX_N_9 RX_P_0 RX_P_1 RX_P_2 RX_P_3 RX_P_4 RX_P_5 RX_P_6 RX_P_7 RX_P_8 RX_P_9 SYS_RES_L TCK TCTL_N TCTL_P TDAT0_N TDAT0_P TDAT1_N TDAT1_P ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Signal UPX_ADD5 UPX_ADD6 UPX_ADD7 UPX_ADD8 UPX_ADD9 UPX_ADD1 UPX_ADD10 UPX_CS_L UPX_DATA0 UPX_DATA1 UPX_DATA2 UPX_DATA3 UPX_DATA4 UPX_DATA5 UPX_DATA6 UPX_DATA7 UPX_DATA8 UPX_DATA9 UPX_DATA10 UPX_DATA11 UPX_DATA12 UPX_DATA13 UPX_DATA14 UPX_DATA15 UPX_DATA16 UPX_DATA17 UPX_DATA18 UPX_DATA19 UPX_DATA20 UPX_DATA21 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Signal VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 4.3.2 Balls Listed in Alphanumeric Order by Ball Location ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Ball Signal B7 TDAT9_P B8 VDD2 B9 UPX_DATA2 B10 GND B11 TX_FAULT_INT B12 VDD2 B13 VDD2 B14 RX_LOS_INT B15 GND B16 UPX_DATA22 B17 VDD2 B18 UPX_DATA28 B19 GND B20 RDAT1_P B21 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Ball Signal G4 UPX_ADD1 G5 TDAT5_P G6 TDAT4_N TDAT3_P G10 GND G11 TDAT15_P G12 UPX_DATA12 G13 UPX_DATA21 G14 UPX_DATA24 G15 MOD_DEF_INT G16 RDAT14_N G17 RDAT10_P G18 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Ball Signal VDD2 M3 GND M4 GND M5 TDAT8_N M6 VDD2 GND M9 VDD2 M10 TCTL_P M11 GND M12 VDD2 M13 VDD2 M14 GND M15 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Ball Signal T22 RX_P_0 T23 GND T24 RX_N_2 VDD2 U3 TX_N_8 U4 GND U5 TX_N_9 U6 VDD2 U7 GND U8 GND U9 TX_DISABLE_6 U10 VDD U11 MOD_DEF_5 U12 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Ball Signal AA19 VDD AA20 NC AA21 GND AA22 NC AA23 VDD2 AA24 TCK AB1 No Ball AB2 MOD_DEF_7 AB3 NC AB4 VDD AB5 NC AB6 GND AB7 GND AB8 NC ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.0 Functional Description 5.1 Media Access Controller 5.1.1 General Description The IXF1110 MAC main functional block consists of a 1000 Mbps Ethernet Media Access Controller (MAC), supporting the following features: • ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1.2.2 Automatic CRC Generation The Automatic CRC Generation is used in conjunction with the padding feature to generate and append a correct CRC to any incoming frame from the SPI4-2 interface. ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1.2.3.4 Filter VLAN Packets This feature is enabled when bit 3 of the VLAN frames received in this mode are marked by the MAC to be dropped. The frame is dropped ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1.3 Flow Control Flow Control is an IEEE 802.3x-defined mechanism for one network node to request that its link partner take a temporary “Pause” in packet transmission. This allows the requesting ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 5 Packet Buffering FIFO SPI4-2 Interface High Water Mark MAC Transfer Threshold * Low Water Mark High Water Mark Low Water Mark TxPauseFr (External strobe) 5.1.3.1.1 Pause Frame Format PAUSE ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 7 PAUSE Frame Format Number of bytes 7 Preamble Note: In the IXF1110 architecture, the TX block of the MAC sets this as the pause multicast address. The RX interface ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 1. The IXF1110 MAC checks the entire frame to verify that valid PAUSE control frame addressed to the Multicast Address 01-80-C2-00-00-01 (as specified in IEEE 802.3, Annex 31B) ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 15 Valid Decodes for TXPAUSEADD[3:0] (Sheet TXPAUSEADD[3:0] 0x8 0x9 0xA 0xB - 0XE 0xF Figure 8 Transmit Pause Control Interface TXPAUSEFR TXPAUSEADD0 TXPAUSEADD1 TXPAUSEADD2 TXPAUSEADD3 This example ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 By default, IXF1110 MAC auto-negotiation is disabled by Register bit 5 (AN_enable) of the Diverse Config ($ Port_Index + 0x18), on page IXF1110 MAC can operate in forced mode, which is ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.1.6 Forced Mode Operation The fiber operation of the MAC can be forced to operated at 1000 Mbps, full duplex without completion of the auto negotiation function. In this mode, the ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 • TXOctetsTotalOK (Addr: Port_Index + 0x40) • TxPkts1519toMaxOctets (Addr: Port_Index + 0x4B) • TxExcessiveLengthDrop (Addr: Port_Index + 0x53) • TXCRCError (Addr: Port_Index + 0x56) The IXF1110 MAC checks the CRC for ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 16 RMON Additional Statistics Registers (Sheet RMON Ethernet Statistics Type Group 1 Statistics etherStatsOctets Counter32 etherStatsPkts Counter32 etherStatsBroadcastPkts Counter32 RX/TXBCPkts etherStatsMulticastPkts Counter32 RX/TXMCPkts etherStatsCRCAlignErrors Counter32 etherStatsOversizePkts Counter32 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 • Good Packets: Error-free packets that have a valid frame length. For example, on Ethernet, good packets are error-free packets that are between 64 octets long and 1518 octets long. They ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 information out-of-band, the transmit and receive interfaces may be de-coupled to operate independently. Figure 9 interface. Figure 9 SPI4-2 Interfacing with the Network Processor or Forwarding Engine TDAT[15:0]_P/N IXF1x10 MAC RDAT[15:0]_P/N ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 17 SPI4-2 Interface Signal Summary (Sheet Signal Name RDCLK_P/N RCTL_P/N RSCLK RSTAT1, RSTAT0 5.2.1 Data Path Transfer of complete packets or shorter bursts is controlled by the ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 new credits are granted until a complete FIFO status cycle has been received and validated by a correct DIP-2 check. This is the only method of operation that can eliminate the ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 18 Control Word Format (Continued) (Sheet Bit Position Label 12 SOP 11:4 ADR 3:0 DIP-4 Table 19 Control Word Definitions Next Bit Word [15:12] Status 0 0000 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 11 shows per-port state transitions at control-word boundaries. At any given time, a port may be active (sending data), paused (not sending data but pending the completion of an outstanding ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2.1.3 DIP4 Figure 12 shows the range over which the Diagonal Interleaved Parity (DIP-4) parity bits are computed. A functional description of calculating the DIP-4 code is given as follows. Assume ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 13 DIP-4 Calculation Algorithm ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2.2.2 CALENDAR_M CALENDAR_M specifies the number of times the calendar port status sequence is repeated between the framing and DIP2 cycle of the calendar sequence. In the IXF1110 MAC, the TX ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.2.2.9 MaxBurst1 MaxBurst1 SPI4-2 parameter specifying the maximum number of 16 byte blocks that may be transmitted when the associated FIFO status indicates “starving”. Bits ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 lines with one training pattern. The sending side of the data path on both the transmit and receive interfaces must schedule the training sequence at least once every DATA_MAX_T cycles. Note: ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 14 FIFO Status State Diagram DIP-2 Disable The FIFO status of each port is encoded in a 2-bit data structure, which is defined in Status Format, on page TSTAT[1]/RSTAT[1] and ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 15 Example of DIP-2 Encoding When the parity bits mimic the “1 1” pattern, the receiving end still frames successfully by syncing ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 20 FIFO Status Format MSB LSB 1 1 Reserved for framing or to indicate a disabled status link. SATISFIED: Indicates that the corresponding port's FIFO is almost full. When SATISFIED ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 check each of the words but only use the first occurrence to clear the DIP-4 error counter. Any DIP-4 error in any of these words is still counted towards the Loss-of-Sync ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.3.3.1 Transmitter Operational Overview The transmit section of the IXF1110 MAC has to serialize the Ten Bit Interface (TBI) data from the IXF1110 MAC section and outputs this data at 1.25 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 setting which corresponds to the normalized power setting of 1.0. This is the default setting of the IXF1110 MAC SerDes interface. Other values listed in the Normalized Driver ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.3.3.4 Selective Power-Down The IXF1110 MAC offers the ability to selectively power-down any of the SerDes ports that are not being used. This is done via Power-Down Ports ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 22 IXF1110 MAC-to-SFP Connections (Sheet IXF1110 MAC SFP Module Pin Names TX_DISABLE_9:0 TX DISABLE TX_FAULT_9:0 RX_LOS_9:0 5.4.3 Functional Descriptions 5.4.3.1 High-Speed Serial Interface These signals are responsible ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.4.3.2.2 TX_FAULT_9:0 These 10 pins are inputs to the IXF1110 MAC. These signals are pulled to a logic Low level by the optical module during normal operation, which indicates no fault ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.4.3.2.7 RX_LOS_INT RX_LOS_INT is a single output, open-drain type signal, and is active Low. A change in state of any of the RX_LOS_0:9 inputs causes this signal to switch Low and ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 2 • Enable bit 2 • Start Access bit • Write Access Complete bit • Read DataValid bit • 4-bit Port Address Select • Read/Write access select ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 3. The state machine uses the data in the Device ID and Register Address fields to build the data frame to be sent to the optical module The I ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 2 5.4.4 Protocol Specifics This section describes the I controlled by an internal state machine. The Serial Clock Line (I with this clock and is driven off the rising ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 19 Start and Stop Definition Timing 2 I C_DATA 2 I C_CLK 5.4.4.4.3 Acknowledge All addresses and data words are serially transmitted to and from the optical module in 8-bit ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 This ensures a clean protocol termination if there is no more data to transfer at the end of the reset cycle. 5.4.4.4.5 Device Addressing 2 All E PROMs in Optical Module ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Timing diagrams and tables can be found in page 102. 5.4.4.4.7 Byte Write Operation The following describes how to achieve the byte write operation: • The IXF1110 MAC generates a start ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 The LED_DATA stream provides data for 30 separate direct drive LEDs and allows three LEDs per MAC port. The three LED pins outlined above are detailed in Descriptions, on page There ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 The operation of the LED Interface in Mode 0 is based on a 36-bit counter loop. The data for each LED is placed in turn on the serial data line and ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 The LED_LATCH signal is required in Mode 1, and is used to latch the data shifted into the shift register chain into the output latches of the 74HC595 device. As seen ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Port Enable ($ 0x500), on page basis. A port must be enabled for the LEDs to operate for that port. If the port is not enabled, the LEDs will be off ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 26 LED Data Decodes (Sheet LED_DATA 5.5.7.1 LED Signaling Behavior The operation in each mode for the decoded LED data in Table 27 LED ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 • Optical Module Block Figure 25 illustrates the I/O for the CPU interface on the IXF1110 MAC. Figure 25 CPU Interface Inputs/Outputs UPX_WR_L UPX_RD_L UPX_CS_L UPX_RDY_L UPX_DATA[31:0] UPX_ADDR[10:0] 5.6.2 Functional Description ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 UPX_CS_L The chip select input when active Low selects IXF1110 MAC for the current cycle. No CPU cycle is recognized without this signal being active. At the end of the cycle, ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 . Figure 26 Read Timing – Asynchronous Interface UPX_ADD[10:0] UPX_CS_L UPX_RD_L UPX_DATA[31:0] UPX_RDY_L 5.6.2.2 Write Access The IXF1110 MAC Write access cycle operation is done in the following order: 1. Chip ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.6.2.3 Timing parameters Timing parameters for the CPU interface are seen in page 106. 5.6.3 Endian The Endian of the CPU interface may be changed to allow connection of various CPUs ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.7.2 TAP State Machine The TAP pins drive a TAP controller, which implements the 16-state machine specified by the IEEE 1149.1 specification. Following power up, the TAP controller must be reset ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.8 Clocks The IXF1110 MAC has system interface reference clocks, SPI4-2 data path input and output clocks, a JTAG input clock, a the unique clock source requirements. 5.8.1 System Interface Reference ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 5.8.3 JTAG Clock The IXF1110 MAC supports JTAG. The source of this clock must meet the following specifications: • 2.5 V CMOS drive • Maximum clock frequency 11 MHz • Maximum ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 6.0 Applications 6.1 Power Supply Sequencing Follow the power-up and power-down sequence described in this section to ensure correct IXF1110 MAC operation. The sequence covers all IXF1110 MAC digital and analog ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 31 Power Sequencing Power Supply VDD, / AVDD1P8_1 AVDD1P8 _2 VDD2, / AVDD2P5_1 AVDD2P5 _2 1. The value of 10 μ s given is a nominal value only. The exact ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 30 Packet Buffering FIFO SPI4-2 Interface High Water Mark MAC Transfer Threshold * Low Water Mark High Water Mark Low Water Mark TxPauseFr (External strobe) Note: The MAC Transfer Threshold ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 The MAC transfer threshold operates on a per packet basis. Once the number of bytes of a packet received in the TX FIFO exceeds the MAC transfer threshold, it will start ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 6.3.1.3.1 Enabling the TX FIFO Drain The TX FIFO drain is enabled using the following occurs when the TX FIFO drain is enabled for a given port: • The TX FIFO ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Pause control frame generation is enabled by default in the 0x12), on page 127. registers needed to set the RX FIFO watermarks. Note: Users should ensure that flow control is enabled ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 6.4.1.2 TX SPI4-2 After reset or power-up, the TX SPI4-2 interface outputs a constant framing pattern on TSTAT until it receives the proper SPI4-2 training pattern from the upstream SPI4-2 device. ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 3. Enable auto-negotiation (if applicable). The device defaults to forced mode not enabled. 4. Once a valid link is established, the TSTAT status bus for that port changes ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 33 SFP-to-IXF1110 MAC Connection (Sheet SFP SFP Pin Pin # Name 1 VeeT NA M24, V23, Y17, R15, 2 TxFault W14, W11, W9, AC5, P8, L2 K22, ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 33 SFP-to-IXF1110 MAC Connection (Sheet SFP SFP Pin Pin # Name N/A N/A B11 N/A N/A B14 N/A N/A G15 ® Cortina Systems IXF1110 10-Port 1000 Mbps ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.0 Electrical Specifications Table 34 through Table 49 on page 115 page 114 represent the target specifications of the following IXF1110 MAC interfaces: • Section 7.3, CPU Timing Specification • Section ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 35 Operating Conditions Parameter Recommended Supply Voltage Operating Current Recommended Operating Temperature Recommended Storage Temperature Power Consumption 1. Typical values are at 25 testing. 2. Refer to the Cortina Systems ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.1 DC Specifications Note: All 3.3 V LVTTL input buffers are 5 V tolerant and all 2.5 V CMOS input buffers are 3.3 V LVTTL level tolerant. Table 36 2.5 V ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 37 LVDS I/O Electrical Characteristics (Sheet Parameter Threshold Hysteresis Differential Input Impedance Output Low Voltage Output High Voltage Differential Output Voltage Delta Differential Output Voltage (Complementary States) ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.3 CPU Timing Specification Figure 32 CPU Port Read Timing uPx_Add[10:0] uPx_Cs uPx_Rd uPx_Data[31:0] uPx_Rdy Figure 33 CPU Port Write Timing uPx_Add[10:0] uPx_Cs uPx_Wr uPx_Data[31:0] uPx_Rdy Table 39 CPU Timing Parameters ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 39 CPU Timing Parameters (Sheet Parameter UPX_DATA[31:0] to UPX_RDY_L Setup Time UPX_DATA[31:0] to UPX_RD_L Hold Time Read UPX_DATA[31:0] Driving Delay UPX_WR_L Width UPX_RDY_L to UPX_WR_L Hold Time ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 40 JTAG Timing Parameters Parameter TCLK Cycle Time TCLK High Time TCLK Low Time TCLK Falling Edge to TDO Valid TMS/TDI Setup to TCLK TMS/TDI Hold from TCLK 1. Typical ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.6 Optical Module Interrupt and I Figure 36 Optical Module Interrupt Timing MOD_DEF_9:0 TX_FAULT_9:0 RX_LOS_9:0 MOD_DEF_Int TX_FAULT_Int RX_LOS_Int Table 42 Optical Module Interrupt Timing Parameters Parameter Change of state on MOD_DEF_9:0 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 2 Figure Write Cycle I 2 C_CLK I 2 C_DATA 2 Table Timing Characteristics Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.7 System Timing Specifications Figure 39 Hardware Reset Timing _______ Sys_Res CPU Access Table 44 Hardware Reset Timing Parameters Parameter Reset Pulse Width Reset Recovery Time 1. Typical values are at ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 45 LED Timing Parameters Parameter LED_CLK Cycle Time LED_CLK High Time LED_CLK Low Time LED_CLK Falling Edge to LED_DATA Valid LED_CLK Rising Edge to LED_LATCH Falling Edge LED_CLK Falling Edge ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 46 Transmitter Characteristics Parameter Transmit differential signal level Transmitter Common Mode Voltage Range Transmit Eye Width Differential signal rise/fall time Differential Output Impedance Transmitter short circuit current Transmitter Frequency Total ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 7.10 SPI4-2 Timing Specifications Figure 42 SPI4-2 Transmit FIFO Status Bus Timing TSCLK TSTAT[1:0] TSTAT[1:0] Table 48 SPI4-2 Transmit FIFO Status Bus Timing Parameters Parameter TSCLK Falling Edge to TSTAT[1:0] Valid ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 49 SPI4-2 Receive FIFO Status Bus Timing Parameters Parameter RSTAT[1:0] Setup to RSCLK Rising Edge (Default operation) RSTAT[1:0] Hold From RSCLK Rising Edge (Default operation) RSTAT[1:0] Setup to RSCLK Falling ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 8.0 Register Definitions 8.1 Introduction This section provides information on the location and functionality of the IXF1110 MAC Control and Status Registers. 8.2 Document Structure This document is structured to give ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 44 Memory Overview 8.4 Per Port Registers The following section covers all of the registers that are replicated in each of the 10 ports in the IXF1110 MAC. These registers ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 45 Register Overview 10 Port Select & Global Registers 8.5 Memory Map Table 51 through Table 59 on page 124 of global control and status registers are used to configure ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 51 MAC Control Register Map (Sheet Config Word ($ Port_Index + 0x16) TX Config Word ($ Port_Index + 0x17) Diverse Config ($ Port_Index + 0x18) RX ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 52 MAC RX Statistics Register Map (Sheet RXCarrierExtendError RXSequenceErrors RXSymbolErrors Read Only; CoR = Clear on Read Write; R/W = Read/Write Table ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 54 Global Status and Configuration Register Map Port Enable ($ 0x500) Reserved Link LED Enable ($ 0x502) Reserved Core Clock Soft Reset ($ 0x504) MAC Soft Reset ($ 0x505) Reserved ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 55 RX Block Register Map (Sheet FIFO Low Watermark Port 6 RX FIFO Low Watermark Port 7 RX FIFO Low Watermark Port 8 RX FIFO Low ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 56 TX Block Register Map (Sheet FIFO Low Watermark Port 4 TX FIFO Low Watermark Port 5 TX FIFO Low Watermark Port 6 TX FIFO Low ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 57 SPI4-2 Block Register Map SPI4-2 RX Burst Size ($ 0x700) SPI4-2 RX Training ($ 0x701) SPI4-2 RX Calendar ($ 0x702) SPI4-2 TX Synchronization ($ 0x703 Read ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 8.5.1 MAC Control Registers Table 60 through Table 76 on page 132 associated with each MAC port. The register address is ‘Port_index + 0x**’, where the port index is set at ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 64 FDFC Address Low ($ Port_Index + 0x08) Bit Name FDFC Address 31:0 Low Read Only; CoR = Clear on Read Write; R/W = Read/Write ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 67 Pause Threshold ($ Port_Index + 0x0E) Bit Name 31:16 Reserved Pause 15:0 Threshold Read Only; CoR = Clear on Read Write; R/W = Read/Write ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 70 Discard Unknown Control Frame ($ Port_Index + 0x15) Bit Name 31:1 Reserved Discard Unknown 0 Control Frame Read Only; CoR = Clear on Read ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 71 RX Config Word ($ Port_Index + 0x16) (Sheet Bit Name 6 Half Duplex 5 Full Duplex 4:0 Reserved Read Only; CoR = Clear ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 73 Diverse Config ($ Port_Index + 0x18) (Sheet Bit Name 5 AN_enable 2 4 Reserved 2 3:2 Reserved 2 1 Reserved 2 0 Reserved ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 74 RX Packet Filter Control ($ Port_Index + 0x19) (Sheet Bit Name Register Description: This register allows for specific packet types to be marked for filtering, and ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 74 RX Packet Filter Control ($ Port_Index + 0x19) (Sheet Bit Name 2 B/Cast Drop En 1 M/Cast Match En 0 U/Cast Match ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 8.5.2 MAC RX Statistics Register Overview The MAC RX Statistics Registers contain the MAC receiver statistic counters and are cleared when read. The software polls these registers and accumulates values to ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 77 MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet Name The total number of packets received (including RxPkts128to255 bad packets) that were [128-255] ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 77 MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet Name Frames bigger than the maximum allowed, with both OK CRC and the integral ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 77 MAC RX Statistics ($ Port_Index + 0x20 - Port_Index + 0x39) (Sheet Name The total number of packets received that are less than 96 bit times, ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 78 MAC TX Statistics ($ Port_Index + 0x40 - Port_Index + 0x58) (Sheet Name TXOctetsTotalOK TXOctetsBad TXUCPkts TXMCPkts TXBCPkts TXPkts64Octets TXPkts65to127Octets TXPkts128to255Octets TXPkts256to511Octets Read ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 78 MAC TX Statistics ($ Port_Index + 0x40 - Port_Index + 0x58) (Sheet Name TXPkts512to1023Octets TXPkts1024to1518Octets TXPkts1519toMaxOctets TXDeferred TXTotalCollisions TXSingleCollisions TXMultipleCollisions TXLateCollisions Read Only; ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 78 MAC TX Statistics ($ Port_Index + 0x40 - Port_Index + 0x58) (Sheet Name TXExcessiveCollisionErrors TXExcessiveDeferralErrors TXExcessiveLengthDrop TXUnderrun TXTagged TXCRCError TXPauseFrames TXFlowControlCollisions Send Read ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 79 Port Enable ($ 0x500) Bit Name Register Description: A control register for each port in the IXF1110 MAC. Port ID = bit position in the register. To make a ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 80 Link LED Enable ($ 0x502) Bit Name Register Description: Per-port bit should be set upon detection of link by system CPU to enable proper operation of the link LEDs. ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 82 MAC Soft Reset ($ 0x505) Bit Name Register Description: Per-port software activated reset of the MAC core. 31:10 Reserved 9 MAC Soft Reset Port 9 8 MAC Soft Reset ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 84 LED Control ($ 0x509) Bit Name Register Description: Globally selects and enables the LED mode. 31-2 Reserved 1 LED Enable 0 LED_SEL_MODE Read Only; CoR = ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 86 LED Fault Disable ($ 0x50B) (Sheet Bit Name LED Fault 5 Disable Port 5 LED Fault 4 Disable Port 4 LED Fault 3 Disable Port 3 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 88 RX FIFO High Watermark Ports 0x580 - 0x589) 2 Name High watermark for RX FIFO port 0. The default value is 1856 bytes. When the ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 89 RX FIFO Low Watermark Ports 0x58A - 0x593) 2 Name Low watermark for RX FIFO port 0. The default value is 1840 bytes. When the ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 90 RX FIFO Number of Frames Removed Ports 0x594 - 0x59D) (Sheet Name This register counts all frames removed from the RX ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 90 RX FIFO Number of Frames Removed Ports 0x594 - 0x59D) (Sheet Name This register counts all frames removed from the RX ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 90 RX FIFO Number of Frames Removed Ports 0x594 - 0x59D) (Sheet Name This register counts all frames removed from the RX ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 91 RX FIFO Port Reset ($ 0x59E) (Sheet Bit Name RXFIFOPort 7 7 Reset RXFIFOPort 6 6 Reset RXFIFOPort 5 5 Reset RXFIFOPort 4 4 Reset RXFIFOPort ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 92 RX FIFO Errored Frame Drop Enable ($ 0x59F) (Sheet Bit Name RX FIFO Errored Frame 7 Drop Enable Port 7 RX FIFO Errored Frame 6 Drop ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 92 RX FIFO Errored Frame Drop Enable ($ 0x59F) (Sheet Bit Name RX FIFO Errored Frame 2 Drop Enable Port 2 RX FIFO Errored Frame 1 Drop ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 93 RX FIFO Overflow Event ($ 0x5A0) (Sheet Bit Name RX FIFO Overflow 3 Event Port 3 RX FIFO Overflow 2 Event Port 2 RX FIFO Overflow ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 94 TX FIFO High Watermark Ports 0x600 - 0x609) (Sheet Name Description High watermark for TX FIFO port 4. The default value ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 95 TX FIFO Low Watermark Ports 0x60A - 0x613) (Sheet Name Description Low watermark for TX FIFO port 0. The default value ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 95 TX FIFO Low Watermark Ports 0x60A - 0x613) (Sheet Name Description Low watermark for TX FIFO port 7. The default value ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 96 TX FIFO MAC Transfer Threshold Ports 0x614 - 0x61D) (Sheet Name Description Sets the value at which the FIFO begins to ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 96 TX FIFO MAC Transfer Threshold Ports 0x614 - 0x61D) (Sheet Name Description Sets the value at which the FIFO begins to ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 97 TX FIFO Overflow Event ($ 0x61E) Bit Name Register Description: This register provides status that a FIFO- full situation has occurred (for example, a FIFO overflow). The bit position ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 98 TX FIFO Drain ($0x620) Bit Name Register Description: This register enables the TX FIFO drain mode for the selected port by holding the TX FIFO for that port in ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 99 TX FIFO Info Out-of-Sequence ($ 0x621) Bit Name Register Description: This register signals when out-of-sequence data is detected in the TX FIFO. Events such as SOP followed by another ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 100 TX FIFO Number of Frames Removed Ports 0-9 ($ 0x622 - 0x62B) Name Description TX FIFO Number This register counts the number of frames of Frames removed on port ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 101 SPI4-2 RX Burst Size ($ 0x700) (Sheet Bit Name 24:16 MaxBurst1 15:9 Reserved 8:0 MaxBurst2 Read Only; CoR = Clear on Read; W ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 103 SPI4-2 RX Calendar ($ 0x702) Bit Name Register Description: SPI4-2 RX interface start-up parameters for FIFO status calendar operation. RX Train Test 31:30 Modes 29 RSCLK_invert 28 TSCLK_invert 27:21 ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 104 SPI4-2 TX Synchronization ($ 0x703) Bit Name Register Description: SPI4-2 synchronization DIP-4 counters. 31:16 DIP4_Errors 15:8 DIP4_UnLock 7:0 DIP4_Lock Read Only; CoR = Clear on Read; ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 106 SerDes Tx Driver Power Level Ports 7-9 ($ 0x785) Bit Name Register Description: Allows selection of various programmable drive strengths on each of the SerDes ports. Note: Refer to ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Table 109 Optical Module Control Ports 0-9 ($ 0x79A) Bit Name Register Description: This register provides access to optical module interrupt enables and sets the TX_DISABLE outputs. 31:13 Reserved 12 RX_LOS_En ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 2 Table 110 I C Control Ports 0-9 ($ 0x79B) (Sheet Bit Name 15 Read/Write 14:11 Device ID Register 10:0 Address Read Only; CoR = ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 9.0 Mechanical Specifications CBGA packages are suited for applications requiring high I/O counts and high electrical performance. They are recommended for high-power applications, having high noise immunity requirements. 9.1 Features • ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 46 RoHS Compliant CBGA Package Diagram (Side View) Note: All dimensions are in mm. ® Cortina Systems IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 9.2 IXF1110 MAC Package Specifics ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 47 RoHS Compliant CBGA Package Diagram (Bottom and Top View) Chip C arrier A01 Cor n er Chip Substra te Note: All dimensions mm. ® Cortina Systems ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 48 Non-RoHS Compliant CBGA Package Diagram (Side View) Note: All dimensions are in mm. ® Cortina Systems IXF1110 10-Port 1000 Mbps Ethernet Media Access Controller 9.2 IXF1110 MAC Package Specifics ...
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IXF1110 MAC Datasheet 250210, Revision 11.0 13 April 2009 Figure 49 Non-RoHS Compliant CBGA Package Diagram (Bottom and Top View) Chip C arrier A01 Cor n er Chip Substra te Note: All dimensions mm. ® Cortina Systems ...
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