LAN7500-ABZJ

Manufacturer Part NumberLAN7500-ABZJ
DescriptionIC USB-10/100/1K ETH CTRL 56QFN
ManufacturerSMSC
LAN7500-ABZJ datasheets
 


Specifications of LAN7500-ABZJ

Mfg Application NotesLAN7500 SchematicDesign ResourcesLAN7500 BOM
Controller TypeEthernet Controller, USB 2.0 to 10/100/1KInterfaceUSB/Serial
Voltage - Supply1.2V, 2.5V, 3.3VOperating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case56-VFQFN Exposed Pad
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Supply-
Other names638-1108  
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Page 13/56

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Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Datasheet
NUM PINS
NAME
PME Mode
PME_MODE_SEL
Select
1
General
Purpose I/O 6
General
1
Purpose I/O 7
General
1
Purpose I/O 8
General
1
Purpose I/O 9
General
1
Purpose I/O
10
General
1
Purpose I/O
11
NUM PINS
NAME
EEPROM
1
Data In
EEPROM
1
Data Out
EEPROM
Chip Select
1
EEPROM
1
Clock
SMSC LAN7500/LAN7500i
Table 2.1 GPIO Pins (continued)
BUFFER
SYMBOL
TYPE
VIS
This pin may serve as the PME_MODE_SEL
input when PME mode of operation is in effect.
(PU)
Refer to
for additional information.
GPIO6
VIS/VO8/
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
VOD8
open-drain output, or a Schmitt-triggered input.
(PU)
GPIO7
VIS/VO8/
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
VOD8
open-drain output, or a Schmitt-triggered input.
(PU)
GPIO8
VIS/VO6/
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
VOD6
open-drain output, or a Schmitt-triggered input.
(PU)
GPIO9
VIS/VO8/
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
VOD8
open-drain output, or a Schmitt-triggered input.
(PU)
GPIO10
VIS/VO8/
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
VOD8
open-drain output, or a Schmitt-triggered input.
(PU)
GPIO11
VIS/VO8/
This General Purpose I/O pin is fully
programmable as either a push-pull output, an
VOD8
open-drain output, or a Schmitt-triggered input.
(PU)
Table 2.2 EEPROM Pins
BUFFER
SYMBOL
TYPE
EEDI
VIS
This pin is driven by the EEDO output of the
external EEPROM.
(PD)
EEDO
VO8
This pin drives the EEDI input of the external
EEPROM.
EECS
VO8
This pin drives the chip select output of the
external EEPROM.
Note:
EECLK
VO8
This pin drives the EEPROM clock of the external
EEPROM.
13
DATASHEET
DESCRIPTION
Chapter 4, "PME Operation," on page 30
DESCRIPTION
The EECS output may tri-state briefly
during power-up. Some EEPROM
devices may be prone to false selection
during this time. When an EEPROM is
used, an external pull-down resistor is
recommended on this signal to prevent
false selection. Refer to your EEPROM
manufacturer’s datasheet for additional
information.
Revision 1.0 (11-01-10)