LAN7500-ABZJ

Manufacturer Part NumberLAN7500-ABZJ
DescriptionIC USB-10/100/1K ETH CTRL 56QFN
ManufacturerSMSC
LAN7500-ABZJ datasheets
 


Specifications of LAN7500-ABZJ

Mfg Application NotesLAN7500 SchematicDesign ResourcesLAN7500 BOM
Controller TypeEthernet Controller, USB 2.0 to 10/100/1KInterfaceUSB/Serial
Voltage - Supply1.2V, 2.5V, 3.3VOperating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case56-VFQFN Exposed Pad
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Supply-
Other names638-1108  
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Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Datasheet
Table 3.4
describes the GPIO PME flags.
BITS
7
GPIO PME Enable
Setting this bit enables the assertion of the
Packet, or PHY Link Up. The host processor may use the
manner analogous to a PCI PME pin.
0 = The device does not support GPIO PME signaling.
1 = The device supports GPIO PME signaling.
Note:
When this bit is 0, the remaining GPIO PME parameters in this flag byte are ignored.
6
GPIO PME Configuration
This bit selects whether the GPIO PME is signaled on the
selected, the duration of the pulse is determined by the setting of the
byte. The level of the signal or the polarity of the pulse is determined by the
this flag byte.
0 = GPIO PME is signaled via a level.
1 = GPIO PME is signaled via a pulse.
Note:
If
GPIO PME Enable
5
GPIO PME Length
When the
GPIO PME Configuration
pulse on the
GPIO5
pin, this bit determines the duration of the pulse.
0 = GPIO PME pulse length is 1.5 mS.
1 = GPIO PME pulse length is 150 mS.
Note:
If
GPIO PME Enable
4
GPIO PME Polarity
Specifies the level of the signal or the polarity of the pulse used for GPIO PME signaling.
0 = GPIO PME signaling polarity is low.
1 = GPIO PME signaling polarity is high.
Note:
If
GPIO PME Enable
3
GPIO PME Buffer Type
This bit selects the output buffer type for GPIO5.
0 = Open drain driver / open source
1 = Push-Pull driver
Note:
Buffer Type = 0, Polarity = 0 implies Open Drain
Buffer Type = 0, Polarity = 1 implies Open Source
Note:
If
GPIO PME Enable
2
GPIO PME WOL Select
Four types of wakeup events are supported; Magic Packet, Perfect DA, PHY Link Up, and Wakeup
Pin(s) assertion. Wakeup Pin(s) are selected via the GPIO Wakeup Enables specified in bytes 1Eh and
1Fh of the EEPROM. This bit selects whether WOL events or Link Up wakeup events are supported.
0 = WOL event wakeup supported.
1 = PHY linkup wakeup supported.
Note:
If WOL is selected, the
the WOL event(s) that will cause a wakeup.
Note:
If
GPIO PME Enable
SMSC LAN7500/LAN7500i
Table 3.4 GPIO PME Flags
DESCRIPTION
GPIO5
pin, as a result of a Wakeup (GPIO) pin, Magic
GPIO5
pin to asynchronously wake up, in a
GPIO5
pin as a level or a pulse. If pulse is
is 0, this bit is ignored.
bit of this flag byte indicates that the GPIO PME is signaled by a
is 0, this bit is ignored.
is 0, this bit is ignored.
is 0, this bit is ignored.
PME Magic Packet Enable
and
PME Perfect DA Enable
is 0, this bit is ignored.
23
DATASHEET
GPIO PME Length
bit of this flag
GPIO PME Polarity
bit of
bits determine
Revision 1.0 (11-01-10)