LAN7500-ABZJ

Manufacturer Part NumberLAN7500-ABZJ
DescriptionIC USB-10/100/1K ETH CTRL 56QFN
ManufacturerSMSC
LAN7500-ABZJ datasheets
 


Specifications of LAN7500-ABZJ

Mfg Application NotesLAN7500 SchematicDesign ResourcesLAN7500 BOM
Controller TypeEthernet Controller, USB 2.0 to 10/100/1KInterfaceUSB/Serial
Voltage - Supply1.2V, 2.5V, 3.3VOperating Temperature0°C ~ 70°C
Mounting TypeSurface MountPackage / Case56-VFQFN Exposed Pad
Lead Free Status / RoHS StatusLead free / RoHS CompliantCurrent - Supply-
Other names638-1108  
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Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller
Datasheet
1.1.6
Host Offloading
The LAN7500/LAN7500i supports a variety of TCP/UDP/IP checksum offloads to reduce the burden
on the host processor. For Ethernet receive frames, the device can be configured to validate the IP
checksum and UDP/TCP checksum. Both IPv4 and IPv6 packets are supported. A raw checksum
across the layer 3 packet can also be provided.
For Ethernet transmitted frames, the device can be configured to calculate the IP checksum and
UDP/TCP checksum. Additionally, Large Send Offload (LSO) is supported to further reduce host CPU
loading.
1.1.7
Power Management
The LAN7500/LAN7500i features four variations of USB suspend: SUSPEND0, SUSPEND1,
SUSPEND2, and SUSPEND3. These modes allow the application to select the ideal balance of remote
wakeup functionality and power consumption.
SUSPEND0: Supports GPIO, “Wake On LAN”, “Magic Packet”, and “PHY Link Up” remote wakeup
events. It, however, consumes the most power.
SUSPEND1: Supports GPIO and “Link Status Change” for remote wakeup events. This suspend
state consumes less power than SUSPEND0.
SUSPEND2: Supports only GPIO assertion for a remote wakeup event. This is the default suspend
mode for the device.
SUSPEND3: Supports GPIO, “Good Packet”, and “PHY Link Up” remote wakeup events. A “Good
Packet” is a received frame that is free of errors and passes certain filtering constraints
independent of those imposed on “Wake On LAN” and “Magic Packet” frames. This suspend state
consumes power at a level similar to the NORMAL state, however, it allows for power savings in
the Host CPU, which greatly exceeds that of the LAN7500/LAN7500i. The driver may place the
device in this state after prolonged periods of not receiving any Ethernet traffic.
1.1.8
EEPROM Controller
The LAN7500/LAN7500i contains an EEPROM controller for connection to an external EEPROM. This
allows for the automatic loading of static configuration data upon pin reset, or software reset. The
EEPROM can be configured to load USB descriptors, USB device configuration, and MAC address.
Custom operation without EEPROM is also provided.
1.1.9
General Purpose I/O
Twelve GPIOs are supported. All GPIOs can serve as remote wakeup events when the
LAN7500/LAN7500i is in a suspended state.
1.1.10
TAP Controller
IEEE 1149.1 compliant TAP Controller supports boundary scan and various test modes.
The device includes an integrated JTAG boundary-scan test port for board-level testing. The interface
consists of four pins (TDO, TDI, TCK and TMS) and includes a state machine, data register array, and
an instruction register. The JTAG pins are described in
interface conforms to the IEEE Standard 1149.1 - 1990 Standard Test Access Port (TAP) and
Boundary-Scan Architecture.
All input and output data is synchronous to the TCK test clock input. TAP input signals TMS and TDI
are clocked into the test logic on the rising edge of TCK, while the output signal TDO is clocked on
the falling edge.
The JTAG logic is reset when the TMS and TDI pins are high for five TCK periods.
SMSC LAN7500/LAN7500i
Table 2.3, “JTAG Pins,” on page
9
DATASHEET
14. The JTAG
Revision 1.0 (11-01-10)