LAN7500I-ABZJ

Manufacturer Part NumberLAN7500I-ABZJ
DescriptionIC USB-10/100/1K ETH CTRL 56QFN
ManufacturerSMSC
LAN7500I-ABZJ datasheets
 


Specifications of LAN7500I-ABZJ

Design ResourcesLAN7500I BOM LAN7500I SchematicController TypeEthernet Controller, USB 2.0 to 10/100/1K
InterfaceUSB/SerialVoltage - Supply1.2V, 2.5V, 3.3V
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case56-VFQFN Exposed PadLead Free Status / RoHS StatusLead free / RoHS Compliant
Current - Supply-Other names638-1109
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PRODUCT FEATURES
Highlights
Single Chip Hi-Speed USB 2.0 to 10/100/1000
Ethernet Controller
10/100/1000 Ethernet MAC with Full-Duplex Support
10/100/1000 Ethernet PHY with HP Auto-MDIX
Integrated USB 2.0 Hi-Speed Device Controller
Integrated USB 2.0 Hi-Speed PHY
Implements Reduced Power Operating Modes
Supports EEPROM-less Operation for Reduced BOM
NetDetach provides automatic USB attach/detach
when Ethernet cable is connected/removed
Target Applications
Embedded Systems / CE Devices
Set-Top Boxes / PVR’s
Networked Printers
USB Port Replicators
Standalone USB to Ethernet Dongles
Test Instrumentation / Industrial
Key Benefits
USB Device Controller
— Fully compliant with USB Specification Revision 2.0
— Supports HS (480 Mbps) and FS (12 Mbps) modes
— Four endpoints supported
— Supports vendor specific commands
— Integrated USB 2.0 PHY
— Remote wakeup supported
High-Performance 10/100/1000 Ethernet Controller
— Fully compliant with IEEE802.3/802.3u/802.3ab
— Integrated Ethernet MAC and PHY
— 10BASE-T, 100BASE-TX, and 1000BASE-T support
— Full- and half-duplex capability (only full-duplex
operation at 1000Mbps)
— Full-duplex flow control
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— 9 KB jumbo frame support
— Automatic payload padding and pad removal
— Loop-back modes
— Supports checksum offloads
(IPv4, IPv6, TCP, UDP)
— Supports Microsoft NDIS 6.2 large send offload
— Supports IEEE 802.1q VLAN tagging
– Ability to add and strip IEEE 802.1q VLAN tags
– VLAN tag based packet filtering (all 4096 VIDs)
SMSC LAN7500/LAN7500i
LAN7500/LAN7500i
Hi-Speed USB 2.0 to
10/100/1000 Ethernet Controller
— Flexible address filtering modes
– 33 exact matches (unicast or multicast)
– 512-bit hash filter for multicast frames
– Pass all multicast
– Promiscuous unicast/multicast modes
– Inverse filtering
– Pass all incoming with status report
— Wakeup packet support
– Perfect DA frame, wakeup frame, magic packet,
broadcast frame, IPv6 & IPv4 TCP SYN
– 8 programmable 128-bit wakeup frame filters
— ARP and NS offload
— PME pin support
— Integrated Ethernet PHY
– Auto-negotiation
– Automatic polarity detection and correction
– HP Auto-MDIX support
– Link status change wake-up detection
— Support for 5 status LEDs
— Supports various statistical counters
Power and I/Os
— Various low power modes
— 12 GPIOs
— Supports bus-powered and self-powered operation
— Variable voltage I/O supply (2.5V/3.3V)
Miscellaneous Features
— EEPROM Controller
— IEEE 1149.1 (JTAG) Boundary Scan
— Requires single 25 MHz crystal
Software
— Windows XP/ Vista / Windows 7 Driver
— Linux Driver
— Win CE Driver
— MAC OS Driver
— EEPROM/Manufacturing Utility for Windows/DOS
— PXE Support
— DOS ODI Driver
Packaging
— 56-pin QFN (8x8 mm) lead-free RoHS compliant
Environmental
— Commercial Temperature Range (0°C to +70°C)
— Industrial Temperature Range (-40°C to +85°C)
DATASHEET
Datasheet
Revision 1.0 (11-01-10)

LAN7500I-ABZJ Summary of contents

  • Page 1

    ... Supports Microsoft NDIS 6.2 large send offload — Supports IEEE 802.1q VLAN tagging – Ability to add and strip IEEE 802.1q VLAN tags – VLAN tag based packet filtering (all 4096 VIDs) SMSC LAN7500/LAN7500i LAN7500/LAN7500i Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller — ...

  • Page 2

    ... LAN7500-ABZJ for 56 pin, QFN lead-free RoHS compliant package (0 to +70°C temp range) LAN7500i-ABZJ for 56 pin, QFN lead-free RoHS compliant package (-40 to +85°C temp range) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © ...

  • Page 3

    ... VDDVARIO & Magnetics = 2.5V .................................................................................... 40 7.3.2.2 VDDVARIO & Magnetics = 3.3V .................................................................................... 40 7.3.3 SUSPEND2 (Self-Powered 7.3.3.1 VDDVARIO & Magnetics = 2.5V .................................................................................... 41 7.3.3.2 VDDVARIO & Magnetics = 3.3V .................................................................................... 41 7.3.4 SUSPEND2 (Bus-Powered 7.3.4.1 VDDVARIO & Magnetics = 2.5V .................................................................................... 42 7.3.4.2 VDDVARIO & Magnetics = 3.3V .................................................................................... 42 7.3.5 Operational . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 SMSC LAN7500/LAN7500i 3 DATASHEET Revision 1.0 (11-01-10) ...

  • Page 4

    ... Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.5.2 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.5.3 Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.5.4 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.5.5 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.5.6 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.6 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller 4 DATASHEET Datasheet SMSC LAN7500/LAN7500i ...

  • Page 5

    ... Figure 7.2 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 7.3 nRESET Power-On Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 7.4 nRESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 7.5 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 7.6 JTAG Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 8.1 LAN7500/LAN7500i 56-QFN Package Figure 8.2 LAN7500/LAN7500i 56-QFN Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . 55 SMSC LAN7500/LAN7500i 5 DATASHEET Revision 1.0 (11-01-10) ...

  • Page 6

    ... Table 7.16 nRESET Power-On Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 7.17 nRESET Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 7.18 EEPROM Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 7.19 JTAG Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 7.20 LAN7500/LAN7500i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 8.1 LAN7500/LAN7500i 56-QFN Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller ...

  • Page 7

    ... Figure 1.1 LAN7500/LAN7500i System Diagram 1.1.1 Overview The LAN7500/LAN7500i is a high performance Hi-Speed USB 2.0 to 10/100/1000 Ethernet controller. With applications ranging from embedded systems, set-top boxes, and PVR’s, to USB port replicators, USB to Ethernet dongles, and test instrumentation, the device is a high performance and cost competitive USB to Ethernet connectivity solution ...

  • Page 8

    ... USB The USB portion of the LAN7500/LAN7500i integrates a Hi-Speed USB 2.0 device controller and USB PHY. The USB device controller contains a USB low-level protocol interpreter which implements the USB bus protocol, packet generation/extraction, PID/Device ID parsing, and CRC coding/decoding, with autonomous error handling. The USB device controller is capable of operating in USB 2.0 Hi-Speed ...

  • Page 9

    ... On LAN” and “Magic Packet” frames. This suspend state consumes power at a level similar to the NORMAL state, however, it allows for power savings in the Host CPU, which greatly exceeds that of the LAN7500/LAN7500i. The driver may place the device in this state after prolonged periods of not receiving any Ethernet traffic. ...

  • Page 10

    ... IEEE 1149.1 operation. 1.1.11 Test Features Read/Write access to internal SRAMs is provided via the devices registers. JTAG based USB BIST is available. 1.1.12 System Software LAN7500/LAN7500i software drivers are available for the following operating systems: Windows XP/ Vista/ Windows 7  Win CE  Linux  ...

  • Page 11

    ... VDD12A 48 VDD12BIAS 49 VDD12PLL 50 TR2N 51 TR2P 52 VDD12A 53 TR3N 54 TR3P 55 VDD12A 56 NOTE: Exposed pad (VSS) on bottom of package must be connected to ground Figure 2.1 LAN7500/LAN7500i 56-QFN Pin Assignments (TOP VIEW) SMSC LAN7500/LAN7500i SMSC LAN7500/LAN7500i 56 PIN QFN (TOP VIEW) VSS 11 DATASHEET EEDO 28 EEDI 27 EECLK 26 GPIO11 25 VDDVARIO 24 ...

  • Page 12

    ... VOD8 open-drain output Schmitt-triggered input. (PU) 12 DATASHEET Datasheet DESCRIPTION This pin is configured as a GPIO by default. This pin is configured as a GPIO by default. This pin is configured as a GPIO by default. This pin is configured as a GPIO by default. Chapter 4, for additional SMSC LAN7500/LAN7500i ...

  • Page 13

    ... NAME EEPROM 1 Data In EEPROM 1 Data Out EEPROM Chip Select 1 EEPROM 1 Clock SMSC LAN7500/LAN7500i Table 2.1 GPIO Pins (continued) BUFFER SYMBOL TYPE VIS This pin may serve as the PME_MODE_SEL input when PME mode of operation is in effect. (PU) Refer to for additional information. GPIO6 VIS/VO8/ ...

  • Page 14

    ... When not used, tie this pin to VSS. When not used, tie this pin to VDDVARIO. DESCRIPTION The functionality of this pin may be swapped to USB DPLUS via the Port Swap bit of Configuration Flags 0. The functionality of this pin may be swapped to USB DMINUS via the Port Swap bit of Configuration Flags 0. SMSC LAN7500/LAN7500i ...

  • Page 15

    ... Channel 2 Ethernet TX/RX 1 Positive Channel 3 Ethernet TX/RX 1 Negative Channel 3 External PHY ETHRBIAS 1 Bias Resistor SMSC LAN7500/LAN7500i Table 2.5 Ethernet PHY Pins BUFFER SYMBOL TYPE XI ICLK External 25 MHz crystal input. Note: XO OCLK External 25 MHz crystal output. TR0P AIO Transmit/Receive Positive Channel 0. TR0N AIO Transmit/Receive Negative Channel 0 ...

  • Page 16

    ... Chapter 6, "Application Diagrams," on and the LAN7500/LAN7500i reference Chapter 6, "Application Diagrams," on and the LAN7500/LAN7500i reference Chapter 6, "Application Diagrams," on and the LAN7500/LAN7500i reference Chapter 6, "Application Diagrams," on and the LAN7500/LAN7500i reference Chapter 6, "Application Diagrams," on and the LAN7500/LAN7500i reference SMSC LAN7500/LAN7500i ...

  • Page 17

    ... GPIO5/PME GPIO11 39 EECLK 40 PME_MODE_SEL EEDI 41 ETHRBIAS EEDO 42 nRESET/ PME_CLEAR EXPOSED PAD MUST BE CONNECTED TO VSS 17 DATASHEET DESCRIPTION Chapter 6, "Application Diagrams," on and the LAN7500/LAN7500i reference and the LAN7500/LAN7500i reference PIN NUM PIN NAME EECS 43 TR0N 44 TR0P 45 VDD12A 46 TR1N 47 TR1P 48 VDD12A 49 VDD12BIAS 50 VDD12PLL ...

  • Page 18

    ... Unless otherwise noted in the pin description, internal pull-downs are always enabled. Note: Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to LAN7500/LAN7500i. When connected to a load that must be pulled low, an external resistor must be added. AI Analog input ...

  • Page 19

    ... Datasheet Chapter 3 EEPROM Controller (EPC) LAN7500/LAN7500i may use an external EEPROM to store the default values for the USB descriptors and the MAC address. The EEPROM controller supports most “93C56 or 93C66” type 256/512 byte EEPROMs. A total of nine address bits are used for connection to the device. ...

  • Page 20

    ... Note: EEPROM byte addresses past 21h can be used to store data for any purpose assuming these addresses are not used for descriptor storage. Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Table 3.1 EEPROM Format (continued) Bits 7:4 Unused. 20 DATASHEET Datasheet SMSC LAN7500/LAN7500i ...

  • Page 21

    ... activity is detected. Note: GPIOEN[1:0] in operation. If only one of the bits is set, then untoward operation and unexpected results may occur. If both bits are clear, then SMSC LAN7500/LAN7500i Configuration Flags 0 byte configuration descriptor exists in the EEPROM, Configuration Flags 0. Table 3.2 Configuration Flags 0 ...

  • Page 22

    ... SUSPEND2, SUSPEND1, and NetDetach. 0 SW_MODE_POL This bit selects the polarity of the 0 = Active low Active high. Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller DESCRIPTION Configuration Flags 1. Table 3.3 Configuration Flags 1 DESCRIPTION SW_MODE SW_MODE pin. 22 DATASHEET Datasheet pin will be asserted. SMSC LAN7500/LAN7500i ...

  • Page 23

    ... WOL event wakeup supported PHY linkup wakeup supported. Note: If WOL is selected, the the WOL event(s) that will cause a wakeup. Note: If GPIO PME Enable SMSC LAN7500/LAN7500i Table 3.4 GPIO PME Flags DESCRIPTION GPIO5 pin result of a Wakeup (GPIO) pin, Magic GPIO5 pin to asynchronously wake up GPIO5 pin as a level or a pulse ...

  • Page 24

    ... Hi-Speed Polling Interval (mS) Configuration Flags 0 Maximum Power (mA) Vendor ID Product ID Note: Refer to the LAN7500/LAN7500i Vendor/Product ID application note for details on proper usage of these fields. 3.3 EEPROM Auto-Load Certain system level resets (USB reset, nRESET, and SRST) cause the EEPROM contents to be loaded into the device. After a reset, the EEPROM controller attempts to read the first byte of data from the EEPROM ...

  • Page 25

    ... EEPROM is formatted. The industrial version of the device is used in the example. OFFSET BYTE 0000h 0008h 0010h 0018h 0020h 0028h 0030h 0038h 0040h 0048h 0050h 0058h 0060h 0068h 0070h 0078h 0080h 0088h 0090h - 00FFh SMSC LAN7500/LAN7500i provide an example of how the contents of a EEPROM are formatted. Table 3.6 Dump of EEPROM Memory VALUE (HEX ...

  • Page 26

    ... Full-Speed Device Descriptor Word Offset (39h) Corresponds to EEPROM Byte Offset 72h Full-Speed Configuration and Interface Descriptor Length (18bytes) Full-Speed Configuration and Interface Descriptor Word Offset (42h) Corresponds to EEPROM Byte Offset 84h GPIO[7:0] Wake Enables - GPIO[7:0] Not Used For Wakeup Signaling 26 DATASHEET Datasheet SMSC LAN7500/LAN7500i ...

  • Page 27

    ... Descriptor Type (String Descriptor - 03h) Manufacturer ID String (“SMSC” in UNICODE) Size of Product Name String Descriptor (18 bytes) Descriptor Type (String Descriptor - 03h) Product Name String (“LAN7500i” in UNICODE) Size of Serial Number String Descriptor (16 bytes) Descriptor Type (String Descriptor - 03h) Serial Number String (“0005123” in UNICODE) ...

  • Page 28

    ... Device Release Number (0100h) Index of Manufacturer String Descriptor Index of Product String Descriptor Index of Serial Number String Descriptor Number of Possible Configurations Size of Full-Speed Configuration Descriptor in bytes (9 bytes) Descriptor Type (Configuration Descriptor - 02h) Total length in bytes of data returned (0027h = 39 bytes) 28 DATASHEET Datasheet SMSC LAN7500/LAN7500i ...

  • Page 29

    ... FF 95h 00 96h - FFh - SMSC LAN7500/LAN7500i DESCRIPTION Number of Interfaces Value to use as an argument to select this configuration Index of String Descriptor describing this configuration Bus powered and remote wakeup enabled Maximum Power Consumption is 500 mA Size of Full-Speed Interface Descriptor in Bytes (9 Bytes) Descriptor Type (Interface Descriptor - 04h) ...

  • Page 30

    ... Chapter 4 PME Operation LAN7500/LAN7500i provides a mechanism for waking up a host system via PME mode of operation. PME signaling is only available while the device is operating in the self powered mode and a properly configured EEPROM is attached. Enable Embedded Controller (EC) Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Figure 4 ...

  • Page 31

    ... Chipset and the Host processor to power up via an Enable signal. The EC interfaces to LAN7500/LAN7500i via four signals. The PME signal is an input to the EC from the device that indicates the occurrence of a wakeup event. The VBUS_DET output of the EC is used to indicate bus power availability ...

  • Page 32

    ... MAC address for Magic Packet  PME signaling configuration: GPIO5 signals PME  GPIO6 is PME_MODE_SEL  Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller = 1 (enabled (PME signaled via level (NA (high level signals event (Push-Pull (Magic Packet wakeup) 32 DATASHEET Datasheet GPIO5 pin) SMSC LAN7500/LAN7500i ...

  • Page 33

    ... False True EC Detects PM E Yes No EC Signals Enable To Host VBUS_DET Set Deasserts Sets PM E_M ODE_SEL = 0 And Asserts PM E_CLEAR LAN7500/LAN7500i Resets And LAN7500/LAN7500i Connects To USB LAN7500/LAN7500i Is In Norm al Figure 4.2 PME Operation 33 DATASHEET Or Via Circuitry Deasserts PM E Bus Operation Revision 1.0 (11-01-10) ...

  • Page 34

    ... GPIO pin asserts, the device automatically attaches to the USB bus. Ethernet SMSC LAN7500/ LAN7500i ...ZZZ Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller 1 Remove Ethernet Cable 2 USB Electricals Detach Battery-powered Netbook PC 3 may enter C3 sleep mode Figure 5.1 LAN7500/LAN7500i Detach 34 DATASHEET Datasheet SMSC LAN7500/LAN7500i ...

  • Page 35

    ... Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Datasheet Ethernet SMSC LAN7500/ LAN7500i SMSC LAN7500/LAN7500i 1 Insert Ethernet Cable 2 USB Electricals Attach LAN7500/LAN7500i 3 enumerates and the driver is loaded Figure 5.2 LAN7500/LAN7500i Attach 35 DATASHEET Revision 1.0 (11-01-10) ...

  • Page 36

    ... LED[0:4] 12 SW_MODE nRESET VBUS_DET Figure 6.1 Simplified Application Diagram Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller LAN7500/LAN7500i TR0P TR0N TR1P TR1N TR2P TR2N TR3P TR3N XI XO TCK TDO TDI TMS 36 DATASHEET Datasheet Magnetics RJ45 25MHz JTAG (optional) SMSC LAN7500/LAN7500i ...

  • Page 37

    ... VDDVARIO (x4) Supply 2.5V – 3.3V C BYPASS x4 ETHRBIAS 8.06K Ohm 1% Figure 6.2 Power Supply & Twisted Pair Interface Diagram SMSC LAN7500/LAN7500i Circuitry within the dotted line is for Channel 0. Duplicate this circuit for Channels 1, 2 and 3. (x4) VDD12A C BYPASS TR0P TR0N 0.022uF 49.9 49 ...

  • Page 38

    ... for commercial version, - +85 Conditions**", Section 7.4, "DC Specifications", or any other applicable section 38 DATASHEET Datasheet 7. +6.0V 7. -0.5V Note 7 +150 o C for industrial version. SMSC LAN7500/LAN7500i C/W C ...

  • Page 39

    ... Table 7.1 SUSPEND0 Current & Power (VDDVARIO & Magnetics = 2.5V) PARAMETER Supply current (VDD33A = 3.3V) Supply current (VDDVARIO = 2.5V) Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL, VDD12PLL, VDD12A = 1.2V) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) SMSC LAN7500/LAN7500i ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A MIN TYPICAL 3.1 453 553 ...

  • Page 40

    ... Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller MIN TYPICAL 3.5 453 556 1231 MIN TYPICAL 0.3 MIN TYPICAL 0.8 114 40 DATASHEET Datasheet MAX UNIT MAX UNIT 0 MAX UNIT SMSC LAN7500/LAN7500i ...

  • Page 41

    ... Table 7.6 SUSPEND2 (Self-Powered) Current & Power (VDDVARIO & Magnetics = 3.3V) PARAMETER Supply current (VDDVARIO, VDD33A = 3.3V) Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL, VDD12PLL, VDD12A = 1.2V) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) SMSC LAN7500/LAN7500i MIN TYPICAL 0.2 2.0 4.4 4.5 ...

  • Page 42

    ... VDD12PLL, VDD12A = 1.2V) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller MIN TYPICAL 0.2 1.0 3.3 3.3 MIN TYPICAL 0.7 1.0 3.4 3.5 42 DATASHEET Datasheet MAX UNIT 0 MAX UNIT SMSC LAN7500/LAN7500i ...

  • Page 43

    ... Power Dissipation (Device and Ethernet components) 10BASE-T Full Duplex (USB High-Speed) Supply current (VDD33A = 3.3V) Supply current (VDDVARIO = 2.5V) Supply current (VDD12CORE, VDD12BIAS, VDD12USBPLL, VDD12PLL, VDD12A = 1.2V) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) SMSC LAN7500/LAN7500i MIN TYPICAL 43 DATASHEET MAX UNIT 6 ...

  • Page 44

    ... VDD12PLL, VDD12A = 1.2V) Power Dissipation (Device Only) Power Dissipation (Device and Ethernet components) Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller MIN TYPICAL 44 DATASHEET Datasheet MAX UNIT 9.8 mA 489 mA 620 mW 1296 mW 7.5 mA 119 mA 168 mW 379 mW 6 101 mW 512 mW SMSC LAN7500/LAN7500i ...

  • Page 45

    ... VO8 Type Buffers Low Output Level V High Output Level V VOD8 Type Buffer Low Output Level V ICLK Type Buffer (XI Input) Low Input Level V High Input Level V SMSC LAN7500/LAN7500i Table 7.11 I/O Buffer Characteristics 2.5V 3.3V MIN TYP TYP -0.3 ILI IHI 0.64 1.15 1.41 ILT 0 ...

  • Page 46

    ... PPH V -950 - -1050 PPL 102 RFS DATASHEET Datasheet UNITS NOTES mV Note 7 Note 7 Note 7.9 % Note 7 Note 7.10 UNITS NOTES mVpk Note 7.11 mVpk Note 7.11 % Note 7.11 5.0 nS Note 7.11 0.5 nS Note 7. Note 7. 1.4 nS Note 7.13 SMSC LAN7500/LAN7500i ...

  • Page 47

    ... Note: The Ethernet TX/RX pin timing adheres to the IEEE 802.3 specification. Refer to the IEEE 802.3 specification for detailed Ethernet timing information. 7.5.1 Equivalent Test Load Output timing specifications assume the 25pF equivalent test load illustrated in unless otherwise specified. OUTPUT SMSC LAN7500/LAN7500i SYMBOL MIN V 2.2 OUT V ...

  • Page 48

    ... Note: The magnetics power supply can be run at 2.5V or 3.3V. Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Table 7.15. Section 7.5.3, "Power-On Reset Timing," on page 49 t pon Figure 7.2 Power Sequence Timing DESCRIPTION 48 DATASHEET Datasheet for power-on reset MIN TYP MAX UNITS SMSC LAN7500/LAN7500i ...

  • Page 49

    ... External power supplies at operational level to nRESET purstd deassertion t External power supplies at at operational level to purstv nRESET valid t nRESET input assertion time rstia Note: nRESET deassertion must be monotonic. SMSC LAN7500/LAN7500i t purstd t t purstv rstia Figure 7.3 nRESET Power-On Timing DESCRIPTION 49 DATASHEET MIN ...

  • Page 50

    ... SYMBOL t nRESET input assertion time rstia Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller for additional information. t rstia Figure 7.4 nRESET Timing Table 7.17 nRESET Timing Values DESCRIPTION 50 DATASHEET Datasheet Section 7.5.3, MIN TYP MAX UNITS 1 μS SMSC LAN7500/LAN7500i ...

  • Page 51

    ... EEDI hold after rising edge of EECLK dhckh t EECLK low to data disable (OUTPUT) ckldis t EEDIO valid after EECS high (VERIFY) cshdv t EEDIO hold after EECS low (VERIFY) dhcsl t EECS low csl SMSC LAN7500/LAN7500i t ckcyc t t ckh ckl cshckh t t ckhinvld dvckh t t dsckh ...

  • Page 52

    ... Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller t tckp t tckhl TCK (Input dov t doinvld TDO (Output) Figure 7.6 JTAG Timing Table 7.19 JTAG Timing Values MIN 66.67 t *0.4 tckp DATASHEET Datasheet Section 1.1.10, "TAP Controller," t tckhl t h MAX UNITS NOTES ns t *0.6 ns tckp SMSC LAN7500/LAN7500i ...

  • Page 53

    ... XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XI/XO). See Table 7.20 LAN7500/LAN7500i Crystal Specifications PARAMETER Crystal Cut Crystal Oscillation Mode ...

  • Page 54

    ... Chapter 8 Package Outline Figure 8.1 LAN7500/LAN7500i 56-QFN Package Table 8.1 LAN7500/LAN7500i 56-QFN Dimensions MIN NOMINAL A 0.70 0.85 A1 0.00 0. D/E 7.85 8.00 D1/E1 7.55 7.75 D2/E2 5.80 5.90 L 0.30 0.40 b 0.18 0. 0.50 BSC Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller ...

  • Page 55

    ... Position tolerance of each terminal and exposed pad is +/- 0. maximum material condition. Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip. 3. The pin 1 identifier may vary, but is always located within the zone indicated. Figure 8.2 LAN7500/LAN7500i 56-QFN Recommended PCB Land Pattern SMSC LAN7500/LAN7500i 55 DATASHEET Revision 1 ...

  • Page 56

    ... Chapter 9 Revision History REVISION LEVEL AND DATE SECTION/FIGURE/ENTRY Rev. 1.0 All (11-01-10) Revision 1.0 (11-01-10) Hi-Speed USB 2.0 to 10/100/1000 Ethernet Controller Table 9.1 Customer Revision History Initial Release. 56 DATASHEET Datasheet CORRECTION SMSC LAN7500/LAN7500i ...